Conrad A Barile

US Patent:

6972209, Dec 6, 2005

Filed:

Nov 27, 2002

Appl. No.:

10/306534

Inventors:

Birendra N. Agarwala - Hopewell Junction NY, US
Conrad A. Barile - Wappingers Falls NY, US
Hormazdyar M. Dalal - LaGrangeville NY, US
Brett H. Engle - Hopewell Junction NY, US
Michael Lane - Cortlandt Manor NY, US
Ernest Levine - Poughkeepsie NY, US
Xiao Hu Liu - Croton-on-Hudson NY, US
Vincent McGahay - Poughkeepsie NY, US
John F. McGrath - Somerville MA, US
Conal E. Murray - Yorktown Heights NY, US
Jawahar P. Nayak - Wappingers Falls NY, US
Du B. Nguyen - Danbury CT, US
Hazara S. Rathore - Stormville NY, US
Thomas M. Shaw - Peekskill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L021/00

US Classification:

438 52, 438 50, 438622, 438623, 438638

Abstract:

A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.

US Patent:

7138714, Nov 21, 2006

Filed:

Feb 11, 2005

Appl. No.:

10/906265

Inventors:

Du B. Nguyen - Danbury CT, US
Birendra N. Agarwala - Hopewell Junction NY, US
Conrad A Barile - Wappingers Falls NY, US
Jawahar P. Nayak - Wappingers Falls NY, US
Hazara S. Rathore - Stormville NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/535

US Classification:

257751, 257E23151

Abstract:

The present invention provides an interconnect structure that includes a diffusion barrier which is positioned within the structure in a fashion that increases the reliability and lifetime of the interconnect structure.

US Patent:

8053257, Nov 8, 2011

Filed:

Apr 2, 2008

Appl. No.:

12/061104

Inventors:

Kaushik Chanda - Fishkill NY, US
Hazara S. Rathore - Stormville NY, US
Paul S. McLaughlin - Poughkeepsie NY, US
Robert D. Edwards - Marlboro NY, US
Lawrence A. Clevenger - LaGrangeville NY, US
Andrew P. Cowley - Wappingers Falls NY, US
Chih-Chao Yang - Glenmont NY, US
Conrad A. Barile - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00

US Classification:

438 17, 257E21521

Abstract:

The invention predicts premature dielectric breakdown in a semiconductor. At least one dielectric breakdown mode is calculated for a layer within chips comprising a semiconductor wafer lot. If only one mode is calculated, that is the best calculated mode. If multiple modes can be calculated, a best mode that most accurately represents dielectric breakdown for the semiconductor wafer lot is determined. Premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard deviation from the best calculated mode.

US Patent:

20060014376, Jan 19, 2006

Filed:

Sep 20, 2005

Appl. No.:

11/230841

Inventors:

Birendra Agarwala - Hopewell Junction NY, US
Conrad Barile - Wappingers Falls NY, US
Hormazdyar Dalal - LaGrangeville NY, US
Brett Engel - Hopewell Junction NY, US
Michael Lane - Cortlandt Manor NY, US
Ernest Levine - Poughkeepsie NY, US
Xiao Liu - Croton-on-Hudson NY, US
Vincent McGahay - Poughkeepsie NY, US
John McGrath - Somerville MA, US
Conal Murray - Yorktown Heights NY, US
Jawahar Nayak - Wappingers Falls NY, US
Du Nguyen - Danbury CT, US
Hazara Rathore - Stormville NY, US
Thomas Shaw - Peekskill NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

H01L 21/4763
H01L 21/44
H01L 21/31

US Classification:

438622000, 438763000, 438672000

Abstract:

A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.

US Patent:

20060281338, Dec 14, 2006

Filed:

Jun 14, 2005

Appl. No.:

11/160213

Inventors:

Kaushik Chanda - Fishkill NY, US
Hazara Rathore - Stormville NY, US
Paul McLaughlin - Poughkeepsie NY, US
Robert Edwards - Marlboro NY, US
Lawrence Clevenger - LaGrangeville NY, US
Andrew Cowley - Wappingers Falls NY, US
Chih-Chao Yang - Poughkeepsie NY, US
Conrad Barile - Wappingers Falls NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

H01L 21/00

US Classification:

438791000, 438005000

Abstract:

The invention predicts premature dielectric breakdown in a semiconductor. At least one dielectric breakdown mode is calculated for the semiconductor wafer. If a one mode is calculated, premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard deviation of a plurality of breakdown voltages within said calculated mode. If multiple modes are calculated, the mode that most accurately represents dielectric breakdown for the semiconductor wafer is determined and premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard of the calculated mode that most accurately represents dielectric breakdown for the semiconductor wafer.

US Patent:

40604276, Nov 29, 1977

Filed:

Apr 5, 1976

Appl. No.:

5/673314

Inventors:

Conrad A. Barile - Wappingers Falls NY
Robert M. Brill - Fishkill NY
John L. Forneris - Lagrangeville NY
Joseph Regh - Wappingers Falls NY

Assignee:

IBM Corporation - Armonk NY

International Classification:

H01L 21265
H01L 21324

US Classification:

148 15

Abstract:

A region in an integrated circuit substrate is formed by first ion implanting impurities of a selected conductivity-determining type into a semiconductor substrate through at least one aperture in a masking electrically insulative layer, and then diffusing a conductivity-determining impurity of the same type through the same aperture into said substrate. The method has particular application when the electrically insulative layer is a composite of two layers, e. g. , a top layer of silicon nitride and a bottom layer of silicon dioxide and the aperture is thus a pair of registered openings respectively through said silicon nitride and silicon dioxide layers, and the aperture through the silicon dioxide layer has greater lateral dimensions than that in the silicon nitride layer to provide an undercut beneath the silicon nitride ion implantation barrier layer.

US Patent:

42434351, Jan 6, 1981

Filed:

Jun 22, 1979

Appl. No.:

6/051078

Inventors:

Conrad A. Barile - Wappingers Falls NY
Goerge R. Goth - Poughkeepsie NY
James S. Makris - Wappingers Falls NY
Arunachala Nagarajan - Wappingers Falls NY
Raj K. Raheja - Hopewell Junction NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2122
H01L 2126

US Classification:

148 15

Abstract:

A very high current ion implanted emitter is formed in a diffused base. Windows are made through the silicon nitride and silicon dioxide layes to both the base contact and the emitter regions using a resist mask. These regions are then protected by resist and the collector contact window is opened through the remainder of the silicon dioxide layer to the reach through region. A screen oxide is then grown in all the exposed areas after the removal of the resist mask. A resist mask is applied which covers only the base and Schottky anode regions. Arsenic is then implanted through the exposed screened areas followed by an etch back step to remove the top damaged layer. With some remaining screen oxide serving as a cap, the emitter drive-in is done.