Mark A. Durlam - Chandler AZ, US Jeffrey H. Baker - Chandler AZ, US Brian R. Butcher - Gilbert AZ, US Mark F. Deherrera - Tempe AZ, US John J. D'Urso - Chandler AZ, US Earl D. Fuchs - Phoenix AZ, US Gregory W. Grynkewich - Gilbert AZ, US Kelly W. Kyler - Mesa AZ, US Jaynal A. Molla - Gilbert AZ, US J. Jack Ren - Phoenix AZ, US Nicholas D. Rizzo - Gilbert AZ, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L029/82 H01L027/14
US Classification:
257422, 257252
Abstract:
A method for fabricating a cladded conductor () for use in a magnetoelectronics device is provided. The method includes providing a substrate () and forming a conductive barrier layer () overlying the substrate (). A dielectric layer () is formed overlying the conductive barrier layer () and a conducting line () is formed within a portion of the dielectric layer (). The dielectric layer () is removed and a flux concentrator () is formed overlying the conducting line ().
Cladded Conductor For Use In A Magnetoelectronics Device And Method For Fabricating The Same
Mark A. Durlam - Chandler AZ, US Jeffrey H. Baker - Chandler AZ, US Brian R. Butcher - Gilbert AZ, US Mark F. Deherrera - Tempe AZ, US John J. D'Urso - Chandler AZ, US Earl D. Fuchs - Phoenix AZ, US Gregory W. Grynkewich - Gilbert AZ, US Kelly W. Kyler - Mesa AZ, US Jaynal A. Molla - Gilbert AZ, US J. Jack Ren - Phoenix AZ, US Nicholas D. Rizzo - Gilbert AZ, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 21/00
US Classification:
438 3, 438652, 438653, 438666, 257E21002
Abstract:
A method for fabricating a cladded conductor () for use in a magnetoelectronics device is provided. The method includes providing a substrate () and forming a conductive barrier layer () overlying the substrate (). A dielectric layer () is formed overlying the conductive barrier layer () and a conducting line () is formed within a portion of the dielectric layer (). The dielectric layer () is removed and a flux concentrator () is formed overlying the conducting line ().
Semiconductor Filter Structure And Method Of Manufacture
Sudhama Shastri - Phoenix AZ, US Ryan Hurley - Gilbert AZ, US Yenting Wen - Chandler AZ, US Emily M. Linehan - Gilbert AZ, US Mark A. Thomas - Negri Sembilan, MY Earl D. Fuchs - Phoenix AZ, US
Assignee:
Semiconductor Components Industries, L. L. C. - Phoenix AZ
International Classification:
H03H 9/00
US Classification:
333186, 257532
Abstract:
In one embodiment, a split well region of one conductivity type is formed in semiconductor substrate of an opposite conductivity type. The split well region forms one plate of a floating capacitor and an electrode of a transient voltage suppression device.
Method Of Forming A High Capacitance Diode And Structure Therefor
David D. Marreiro - Phoenix AZ, US Sudhama C. Shastri - Phoenix AZ, US Gordon M. Grivna - Meza AZ, US Earl D. Fuchs - Phoenix AZ, US
Assignee:
Semiconductor Components Industries, LLC - Phoenix AZ
International Classification:
H01L 21/20
US Classification:
438380, 438983, 257603, 257E29335, 257E21356
Abstract:
In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.
Method Of Forming A High Capacitance Diode And Structure Therefor
David D. Marreiro - Phoenix AZ, US Sudhama C. Shastri - Phoenix AZ, US Gordon M. Grivna - Mesa AZ, US Earl D. Fuchs - Phoenix AZ, US
Assignee:
Semiconductor Components Industries, LLC - Phoenix AZ
International Classification:
H01L 21/20
US Classification:
257603, 257E29335, 257E21356, 438380, 438963
Abstract:
In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.
David D. Marreiro - Phoeniz AZ, US Sudhama C. Shastri - Phoenix AZ, US Gordon M. Grivna - Mesa AZ, US Earl D. Fuchs - Phoenix AZ, US
Assignee:
Semiconductor Components Industries, LLC - Phoenix AZ
International Classification:
H01L 21/20
US Classification:
438380, 438983, 257603, 257E29335, 257E21356
Abstract:
In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.
An improved method and structure for high voltage semiconductor devices capable of blocking voltages of the order of 1000 volts and greater is described. In a preferred embodiment, a blanket P layer is formed in an N. sup. - epi-layer on an N. sup. + substrate. An annular groove is etched through the blanket P layer into the N. sup. - epi-layer. The bottom of the groove is doped N. sup. + using the same mask as for the first groove etch. A second groove is formed inside of and partly overlapping the first groove and extending to a greater depth than the first groove, but not through the epi-layer. The second groove is fileld with passivating material, metal electrodes are applied to the P. sup. + region and the N. sup. + substrate, and the devices separated at the N. sup.
Method Of Making High Voltage Semiconductor Device
An improved method and structure for high voltage semiconductor devices capable of blocking voltages of the order of 1000 volts and greater is described. In a preferred embodiment, a blanket P layer is formed in an N. sup. - epi-layer on an N. sup. + substrate. An annular groove is etched through the blanket P layer into the N. sup. - epi-layer. The bottom of the groove is doped N. sup. + using the same mask as for the first groove etch. A second groove is formed inside of and partly overlapping the first groove and extending to a greater depth than the first groove, but not through the epi-layer. The second groove is filled with passivating material, metal electrodes are applied to the P. sup. + region and the N. sup. + substrate, and the devices separated at the N. sup.
Resumes
New Product Development Engineer At On Semiconductor
ON Semiconductor (Public Company; Semiconductors industry): New Product Development Engineer, (September 2005-Present) New product development/device engineer for EMI filters and protection devices in the Zener/Rectifier Wafer Fab. Responsible for the definition of the process ...