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John A Bracchitta

age ~65

from Nashua, NH

Also known as:
  • John Bracchitta
  • John Brachitta

John Bracchitta Phones & Addresses

  • Nashua, NH
  • Bedford, NH
  • Underhill, VT
  • 53 Moss Glen Ln, South Burlington, VT 05403
  • Colchester, VT
  • S Burlington, VT

Us Patents

  • Method For Forming Pillar Cmos

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  • US Patent:
    6344381, Feb 5, 2002
  • Filed:
    May 1, 2000
  • Appl. No.:
    09/561670
  • Inventors:
    John A. Bracchitta - South Burlington VT
    Jack A. Mandelman - Stormville NY
    Stephen A. Parke - Nampa ID
    Matthew R. Wordeman - Mahopac NY
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    H01L 218238
  • US Classification:
    438199, 438222, 438223, 438227, 438229, 438231
  • Abstract:
    A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N and P diffusions in the P and N wells respectively. A unitary pillar of the epitaxial silicon is grown on the substrate having a base at the substrate overlying both the N and P wells and preferably extending at least from said N diffusion to said P diffusion in said substrate. The pillar terminates at a distal end. An N well is formed on the side of the pillar overlying the N well in the substrate and a P well is formed on the side of the distal end of the pillar overlying the P well on the substrate and abuts the N well in the pillar. A P diffusion is formed in the N well in the pillar adjacent the distal end and a N diffusion is formed in the P well in the pillar adjacent the distal end. A gate insulator dioxide is formed over both sides of the pillar and gate electrodes are formed over the gate insulators.
  • Intellectual Property Management Method And Apparatus

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  • US Patent:
    7630915, Dec 8, 2009
  • Filed:
    Jun 14, 2006
  • Appl. No.:
    11/424003
  • Inventors:
    John Anthony Bracchitta - South Burlington VT,
    Patricia McGuiness Marmillion - Colchester VT,
    Bernadette Ann Pierson - South Hero VT,
    Henry Charles Rickers - Poughkeepsie NY,
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    G06F 17/60
  • US Classification:
    705 8
  • Abstract:
    An intellectual property management facility for proactively creating, developing and managing an intellectual property portfolio includes: determining available resource capacity for an intellectual property activity in a tracking system; assigning technical attributes to the activity in the tracking system; apportioning resource capacity for the activity by technical attribute based on the value assigned to each of the technical attributes and based on available resource capacity; obtaining actual resource usage by technical attribute from the tracking system; and managing resource allocation for the intellectual property activity by determining the difference between the actual resource usage and the resource allocation by technical attribute.
  • Pillar Cmos Structure

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  • US Patent:
    62556991, Jul 3, 2001
  • Filed:
    May 1, 2000
  • Appl. No.:
    9/561676
  • Inventors:
    John A. Bracchitta - South Burlington VT
    Jack A. Mandelman - Stormville NY
    Stephen A. Parke - Nampa ID
    Matthew R. Wordeman - Mahopac NY
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    H01L 2976
    H01L 2362
  • US Classification:
    257369
  • Abstract:
    A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N. sup. + and P. sup. + diffusions in the P and N wells respectively. A unitary pillar of the epitaxial silicon is grown on the substrate having a base at the substrate overlying both the N and P wells and preferably extending at least from said N. sup. + diffusion to said P. sup. + diffusion in said substrate. The pillar terminates at a distal end. An N well is formed on the side of the pillar overlying the N well in the substrate and a P well is formed on the side of the distal end of the pillar overlying the P well on the substrate and abuts the N well in the pillar. A P. sup. + diffusion is formed in the N well in the pillar adjacent the distal end and a N. sup. + diffusion is formed in the P well in the pillar adjacent the distal end.
  • Damascene Nvram Cell And Method Of Manufacture

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  • US Patent:
    60603585, May 9, 2000
  • Filed:
    Oct 21, 1997
  • Appl. No.:
    8/955209
  • Inventors:
    John A. Bracchitta - South Burlington VT
    Jeffrey B. Johnson - Essex Junction VT
    Glen L. Miles - Essex Junction VT
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    H01L 21336
  • US Classification:
    438259
  • Abstract:
    Recessing the floating gate of a NVRAM cell within a substrate or semiconductor layer between isolation structures permits manufacture by a simplified self-aligned process of high yield and economy while supporting maximum integration density and reducing or eliminating severe topography of the control gate connections which are formed in strips having a generally planar lower surface and which are of improved robustness and potentially fine pitch. Impurity implants are facilitated by thicknesses of various material present during portions of the process and in various combinations which may be advantageously exploited to obtain tailoring of impurity concentrations and profiles of both NVRAM cells and damascene field effect transistors formed by similar and compatible processes.
  • Pillar Cmos Structure

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  • US Patent:
    61001236, Aug 8, 2000
  • Filed:
    Jan 20, 1998
  • Appl. No.:
    9/009456
  • Inventors:
    John A. Bracchitta - South Burlington VT
    Jack A. Mandelman - Stormville NY
    Stephen A. Parke - Nampa ID
    Matthew R. Wordeman - Mahopac NY
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    H01L 218238
  • US Classification:
    438199
  • Abstract:
    A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N. sup. + and P. sup. + diffusions in the P and N wells respectively. A unitary pillar of the epitaxial silicon is grown on the substrate having a base at the substrate overlying both the N and P wells and preferably extending at least from said N. sup. + diffusion to said P. sup. + diffusion in said substrate. The pillar terminates at a distal end. An N well is formed on the side of the pillar overlying the N well in the substrate and a P well is formed on the side of the distal end of the pillar overlying the P well on the substrate and abuts the N well in the pillar. A P. sup. + diffusion is formed in the N well in the pillar adjacent the distal end and a N. sup. + diffusion is formed in the P well in the pillar adjacent the distal end.
  • Electrically Alterable Antifuse Using Fet

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  • US Patent:
    61304697, Oct 10, 2000
  • Filed:
    Apr 24, 1998
  • Appl. No.:
    9/066122
  • Inventors:
    John A. Bracchitta - South Burlington VT
    Wilbur D. Pricer - Charlotte VT
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    H01L 2900
    H01L 2904
    H01L 2974
    H01L 2358
  • US Classification:
    257530
  • Abstract:
    An integrated circuit and fabrication method for an antifuse structure that includes a shallow trench oxide isolation region disposed in a silicon substrate, the oxide in the trench having a top surface recessed below the surface of the substrate to form sharp corners at each side of the trench. The substrate includes diffusion regions adjacent to the sharp corners, electrical insulation layers over the diffusion regions, and an electrical conductor is disposed over the recessed oxide in the trench. When voltage is applied on the electrical conductor, a high field point is produced at the sharp corners causing the electrical insulation layer at the corners to break down and create a short circuit between the electrical conductor and the diffusions, thus providing a fuse function.
  • Method Of Making A Diffused Lightly Doped Drain Device With Built In Etch Stop

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  • US Patent:
    55189458, May 21, 1996
  • Filed:
    May 5, 1995
  • Appl. No.:
    8/435262
  • Inventors:
    John A. Bracchitta - South Burlington VT
    Gabriel Hartstein - Burlington VT
    Stephen A. Mongeon - Essex Junction VT
    Anthony C. Speranza - Austin TX
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    H01L 21265
  • US Classification:
    437 44
  • Abstract:
    A method of fabricating a lightly doped drain MOSFET device with a built in etch stop is disclosed. After forming a gate electrode on a substrate through conventional methods, a conformal doped layer is deposited on the gate electrode. A conformal layer of nitride is then deposited on the conformal doped layer. The nitride layer is etched, with the etch stopping on the conformal doped layer, thereby forming nitride spacers. Deep source and drain regions are formed by either ion implantation or diffusion. The device is then heat treated so that light diffusion occurs under the nitride spacers and heavy diffusion occurs outside the spacer region. The method is applicable to N-substrate (P-channel), P-substrate (N-channel), and complementary metal oxide semiconductor (CMOS) devices.
  • Polysilicon Capacitor Having Large Capacitance And Low Resistance And Process For Forming The Capacitor

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  • US Patent:
    62618954, Jul 17, 2001
  • Filed:
    Jan 4, 1999
  • Appl. No.:
    9/225043
  • Inventors:
    James W. Adkisson - Jericho VT
    John A. Bracchitta - South Burlington VT
    Jed H. Rankin - Burlington VT
    Anthony K. Stamper - Williston VT
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    H01L 218242
  • US Classification:
    438240
  • Abstract:
    A process for forming capacitors in a semiconductor device. In one embodiment, a first insulating layer is deposited on the semiconductor device; a trench is formed in the insulating layer; a first low resistance metal layer is formed covering the interior surface of the trench; a first polysilicon layer is formed over the first low resistance metal layer; a first dielectric layer is formed over the first polysilicon layer; a second polysilicon layer is formed over the first dielectric layer; a second low resistance metal layer is formed over the second polysilicon layer; a third polysilicon layer is formed over the second low resistance metal layer; a second dielectric layer is formed over the third polysilicon layer; a fourth polysilicon layer is formed over the second dielectric layer; a third low resistance metal layer is formed over the fourth polysilicon layer until the trench is filled; the semiconductor device is planarized until the first, second and third low resistance metal layers are exposed above the trench; finally, capacitor leads are formed to the first, second, and third low resistance metal layers.

Myspace

John Bracchitta Photo 1

John Bracchitta

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Locality:
Shelton (ugh), CONNECTICUT
Birthday:
1944

Googleplus

John Bracchitta Photo 2

John Bracchitta

Education:
Wheaton College - English
About:
Sometimes I say things about stuff, usually more eloquently....
Tagline:
Kenny F'n Powers
Bragging Rights:
Was once invited to join Google+. That was pretty sweet

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Massimo John Bracchitta

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Friends:
Andrea Bracchitta, Alessandro Chessari, Carmelo Costa, Valeria Distefano

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