Robert L Stephenson

Author:

Robert E. Stephenson

ISBN #:

0155126466

Author:

Robert B. Stephenson

ISBN #:

0752400738

Author:

Robert C. Stephenson

ISBN #:

0486418197

Author:

Robert Weston Stephenson

ISBN #:

0853137773

Author:

Robert Stephenson

ISBN #:

0395200628

Author:

Robert Stephenson

ISBN #:

0811426033

Author:

Robert Stephenson

ISBN #:

0811426068

US Patent:

7045377, May 16, 2006

Filed:

Apr 1, 2005

Appl. No.:

11/096828

Inventors:

Robert J. Mears - Wellesley MA, US
Robert John Stephenson - Newton Upper Falls MA, US

Assignee:

RJ Mears, LLC - Waltham MA

International Classification:

H01L 21/00

US Classification:

438 45, 438 47, 438172, 257 15

Abstract:

A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The method may further include forming a semiconductor layer adjacent the superlattice and comprising at least one first region therein including a first conductivity type dopant. At least one second region may be formed in the superlattice including a second conductivity type dopant to define, with the at least one first region, at least one semiconductor junction.

US Patent:

7045813, May 16, 2006

Filed:

Apr 1, 2005

Appl. No.:

11/097433

Inventors:

Robert J. Mears - Wellesley MA, US
Robert John Stephenson - Newton Upper Falls MA, US

Assignee:

RJ Mears, LLC - Waltham MA

International Classification:

H01L 31/72

US Classification:

257 18, 257 15

Abstract:

A semiconductor device may include a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The superlattice may further include at least one pair of oppositely-doped regions therein defining at least one semiconductor junction.

US Patent:

7109052, Sep 19, 2006

Filed:

Sep 9, 2004

Appl. No.:

10/936920

Inventors:

Robert J. Mears - Wellesley MA, US
Robert John Stephenson - Newton Upper Falls MA, US

Assignee:

RJ Mears, LLC - Waltham MA

International Classification:

H01L 21/00

US Classification:

438 31, 438223

Abstract:

A method for making an integrated circuit may include forming at least one active optical device and a waveguide coupled thereto. The waveguide may include a superlattice including a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

US Patent:

7153763, Dec 26, 2006

Filed:

May 25, 2005

Appl. No.:

11/136834

Inventors:

Marek Hytha - Brookline MA, US
Robert John Stephenson - Newton Upper Falls MA, US
Scott A. Kreps - Southborough MA, US

Assignee:

RJ Mears, LLC - Waltham MA

International Classification:

H01L 21/3205

US Classification:

438604, 438 3, 438240, 438938, 438110, 257 9, 257E29298

Abstract:

A method for making a semiconductor device may include forming a superlattice including a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include performing at least one anneal prior to completing forming of the superlattice.

US Patent:

7227174, Jun 5, 2007

Filed:

Apr 1, 2005

Appl. No.:

11/097588

Inventors:

Robert J. Mears - Wellesley MA, US
Robert John Stephenson - Newton Upper Falls MA, US

Assignee:

RJ Mears, LLC - Waltham MA

International Classification:

H01L 29/06

US Classification:

257 15, 257 14, 257E33009

Abstract:

A semiconductor device may include a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The semiconductor device may further include a semiconductor layer adjacent the superlattice and comprising at least one first region therein including a first conductivity type dopant. The superlattice may also include at least one second region therein including a second conductivity type dopant to define, with the at least one first region, at least one semiconductor junction.

US Patent:

7229902, Jun 12, 2007

Filed:

Apr 1, 2005

Appl. No.:

11/097612

Inventors:

Robert J. Mears - Wellesley MA, US
Robert John Stephenson - Newton Upper Falls MA, US

Assignee:

RJ Mears, LLC - Waltham MA

International Classification:

H01L 21/20
H01L 21/36

US Classification:

438496, 438197, 257E33055

Abstract:

A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming at least one pair of oppositely-doped regions in the superlattice defining at least one semiconductor junction.

US Patent:

7279699, Oct 9, 2007

Filed:

Sep 9, 2004

Appl. No.:

10/937071

Inventors:

Robert J. Mears - Wellesley MA, US
Robert John Stephenson - Newton Upper Falls MA, US

Assignee:

RJ Mears, LLC - Waltham MA

International Classification:

G02F 1/017

US Classification:

257 15, 257 17, 257 18, 257 19, 257 21, 385129, 385131

Abstract:

An integrated circuit may include at least one active optical device and a waveguide coupled thereto. The waveguide may include a superlattice including a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

US Patent:

7432524, Oct 7, 2008

Filed:

Sep 9, 2004

Appl. No.:

10/936903

Inventors:

Robert J. Mears - Wellesley MA, US
Robert John Stephenson - Newton Upper Falls MA, US

Assignee:

MEARS Technologies, Inc. - Waltham MA

International Classification:

H01L 29/06

US Classification:

257 15, 257 13, 257 21

Abstract:

An integrated circuit may include at least one active optical device including a superlattice including a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The integrated circuit may further include a waveguide coupled to the at least one active optical device.