Walter U Kuenast

US Patent:

57652163, Jun 9, 1998

Filed:

Jun 17, 1996

Appl. No.:

8/665927

Inventors:

Paul M. Astrachan - Austin TX
Peter C. Curtis - Austin TX
Donald C. Anderson - Austin TX
Walter U. Kuenast - Austin TX
Kenneth C. Weng - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1200

US Classification:

711214

Abstract:

A data processor (40) includes source (60) and destination (61) address generation units (AGUs) to update source and destination addresses for efficient digital signal processing (DSP) functions. The data processor (40) includes an instruction decoder (41) which recognizes a bit movement instruction, which is frequently encountered in data interleaving operations. In response to the bit movement instruction, the instruction decoder (41) causes the source (60) and destination (61) AGUs to update their present addresses using variable offset values. The instruction decoder (41) further causes a bus controller (44) to convert these bit addresses to corresponding operand addresses and bit fields. The bus controller (44) accesses source and destination operands using the operand addresses. The instruction decoder (41) then causes an execution unit (45) to transfer a bit from the source operand indicated by the source bit field to a bit position of the destination operand indicated by the destination bit field.

US Patent:

56529031, Jul 29, 1997

Filed:

Nov 1, 1994

Appl. No.:

8/332971

Inventors:

Walter U. Kuenast - Austin TX
Donald C. Anderson - Austin TX
Peter C. Curtis - Austin TX
Richard L. Greene - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 900

US Classification:

395800

Abstract:

A DSP co-processor (72) that is used on an integrated circuit (24) that provides multiple communication functions is accomplished by providing a data bus interface (320), a sequencer (328), internal memory (33), and a data core (322). The sequencer (328) stores in a hardware format a signal processing algorithm (332) and, upon receipt of an operational command, provides address control signals (334) and operation control signals (336) to the data core (322). The data core (322), which includes an address generation unit (340) and an arithmetic unit (344), executes, via the arithmetic unit, operational instructions of the signal processing algorithm to produce resultant signals from the input samples, the intermediate resultants, and the algorithm co-efficients.

US Patent:

56218001, Apr 15, 1997

Filed:

Nov 1, 1994

Appl. No.:

8/333152

Inventors:

Walter U. Kuenast - Austin TX
Paul M. Astrachan - Austin TX
Donald C. Anderson - Austin TX
Peter C. Curtis - Austin TX
Jose G. Corleto - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04L 900

US Classification:

380 49

Abstract:

An integrated circuit that provides multiple communication functions is accomplished by providing an integrated circuit (24) that includes memory (70) which stores an audio code algorithm, echo cancellation information, a modem processing algorithm, and audio data. The memory (70) is coupled via a data bus (50) to a signal converter (56), a central processing unit (58), and a first co-processor (72). The signal converter (56) provides an analog-to-digital input port (78) and a digital-to-analog output port (80) for the integrated circuit (24), wherein the audio data is received via the analog-to-digital input port (78). The central processing unit (58) executes at least a first portion of the audio coding algorithm upon the audio data and executes a first portion of the modem processing algorithm, while the first co-processor (72) executes an echo cancellation algorithm.

US Patent:

50273698, Jun 25, 1991

Filed:

Mar 26, 1990

Appl. No.:

7/498655

Inventors:

Walter U. Kuenast - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03H 730

US Classification:

375 14

Abstract:

A communications system receives data which is transmitted in pulse form but which is distorted by a communications medium and quantizes the data. Due to the distortion, a quantization error exists. A Decision Feedback Equalizer (DFE) is used to remove the error thru a convergence technique. The DFE has two separate portions which each function as an individual DFE having a different number of taps and different adaptive tap sizes. A first DFE portion operates alone to rapidly coverge the measured error to a predetermined threshold. A control circuit is used to determine when the threshold is reached and to activate the second DFE portion for rapid further error convergence.