Yan Y Ye

US Patent:

6348126, Feb 19, 2002

Filed:

Aug 11, 2000

Appl. No.:

09/636699

Inventors:

Hiroji Hanawa - Sunnyvale CA
Yan Ye - Campbell CA
Kenneth S Collins - San Jose CA
Kartik Ramaswamy - Santa Clara CA
Andrew Nguyen - San Jose CA
Tsutomu Tanaka - Santa Clara CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 2100

US Classification:

156345, 118723 I

Abstract:

A plasma reactor for processing a workpiece includes a chamber adapted to accept processing gases in an evacuated environment including a workpiece support, a hollow conduit defining a wall of the chamber, and having respective ends opening adjacent opposite sides of the workpiece support, and a chamber wall portion in facing relationship to the workpiece support and defining a workpiece processing zone therebetween, the processing zone and the interior of the conduit forming a torroidal interior path, and an RF energy applicator irradiating gas within the chamber to maintain a plasma within the torroidal interior path.

US Patent:

6352049, Mar 5, 2002

Filed:

Jul 20, 1998

Appl. No.:

09/119417

Inventors:

Gerald Yin - Cupertino CA
Hong Ching Shan - San Jose CA
Peter Loewenhardt - San Jose CA
Chii Lee - Fremont CA
Yan Ye - Campbell CA
Xueyan Qian - Milpitas CA
Songlin Xu - Fremont CA
Arthur Chen - Fremont CA
Arthur Sato - San Jose CA
Michael Grimbergen - Redwood City CA
Diana Ma - Saratoga CA
John Yamartino - Palo Alto CA
Chun Yan - Santa Clara CA
Wade Zawalski - Sunnyvale CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23E 1648

US Classification:

118723MP, 118723 AN, 118723 IR, 156345

Abstract:

The present invention provides an apparatus and method, for plasma assisted processing of a workpiece, which provides for separate control of species density within a processing plasma. The present invention has a processing chamber and at least one collateral chamber. The collateral chamber is capable of generating a collateral plasma and delivering it to the processing chamber. To control the densities of the particle species within the processing chamber the present invention may have: a filter interposed between the collateral chamber and the processing chamber, primary chamber source power, several collateral chambers providing separate inputs to the processing chamber, or combinations thereof. Collateral plasma may be: filtered, combined with primary chamber generated plasma, combined with another collateral plasma, or combinations thereof to separately control the densities of the species comprising the processing plasma.

US Patent:

6352081, Mar 5, 2002

Filed:

Jul 9, 1999

Appl. No.:

09/350802

Inventors:

Danny Chien Lu - San Jose CA
Allen Zhao - Mountain View CA
Peter Hsieh - San Jose CA
Hong Shih - Walnut Creek CA
Li Xu - Santa Clara CA
Yan Ye - Saratoga CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

B08B 900

US Classification:

134 221, 134 11, 134 11, 134 2214, 134 30, 134 26, 216 67, 216 74, 216 78, 438905

Abstract:

The present invention is a method for removing deposited etch byproducts from surfaces of a semiconductor processing chamber after a copper etch process. The method of the invention comprises the following general steps: (a) an oxidation step, in which interior surfaces of the processing chamber are contacted with an oxidizing plasma; (b) a first non-plasma cleaning step, in which interior surfaces of the processing chamber are contacted with an H hfac-comprising gas; and (c) a second cleaning step, in which interior surfaces of the processing chamber are contacted with a plasma containing reactive fluorine species, whereby at least a portion of the copper etch byproducts remaining after step (b) are volatilized into gaseous species, which are removed from the processing chamber. The method of the invention is preferably performed at a chamber wall temperature of at least 150Â C. in order to achieve optimum cleaning of the chamber at the chamber operating pressures typically used during the cleaning process.

US Patent:

6372633, Apr 16, 2002

Filed:

Jul 8, 1998

Appl. No.:

09/111657

Inventors:

Dan Maydan - Los Altos Hills CA
Ashok K. Sinha - Palo Alto CA
Zheng Xu - Foster City CA
Liang-Yu Chen - Foster City CA
Roderick Craig Mosely - Pleasanton CA
Daniel Carl - Pleasanton CA
Diana Xiaobing Ma - Saratoga CA
Yan Ye - Campbell CA
Wen Chiang Tu - Sunnyvale CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 214763

US Classification:

438637, 257763

Abstract:

The present invention provides a method and apparatus for forming reliable interconnects in which the overlap of the line over the plug or via is minimized or eliminated. In one aspect, a barrier plug comprised of a conductive material, such as tungsten, is deposited over the via to provide an etch stop during line etching and to prevent diffusion of the metal, such as copper, into the surrounding dielectric material if the line is misaligned over the via. Additionally, the barrier plug prevents an overall reduction in resistance of the interconnect and enables reactive ion etching to be employed to form the metal line. In another aspect, reactive ion etching techniques are employed to selectively etch the metal line and the barrier layer to provide a controlled etching process which exhibits selectivity for the metal line, then the barrier and then the via or plug.

US Patent:

6410449, Jun 25, 2002

Filed:

Aug 11, 2000

Appl. No.:

09/636436

Inventors:

Hiroji Hanawa - Sunnyvale CA
Yan Ye - Campbell CA
Kenneth S Collins - San Jose CA
Kartik Ramaswamy - Santa Clara CA
Andrew Nguyen - San Jose CA
Tsutomu Tanaka - Santa Clara CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21302

US Classification:

438706, 438710, 438711

Abstract:

A method of processing a workpiece in a plasma reactor includes establishing a torroidal path for a plasma current to flow that passes near and transverse to the surface of said workpiece, maintaining a plasma current in the torroidal path by applying RF power to a portion of the torroidal path away from the surface of the workpiece, and increasing the ion density of the plasma current in the vicinity of the workpiece by constricting the area of a portion of the torroidal path overlying the workpiece.

US Patent:

6453842, Sep 24, 2002

Filed:

Aug 11, 2000

Appl. No.:

09/636700

Inventors:

Hiroji Hanawa - Sunnyvale CA
Yan Ye - Campbell CA
Kenneth S Collins - San Jose CA
Kartik Ramaswamy - Santa Clara CA
Andrew Nguyen - San Jose CA
Tsutomu Tanaka - Santa Clara CA

Assignee:

Applied Materials Inc. - Santa Clara CA

International Classification:

C23C 1600

US Classification:

118723I, 118723 IR, 118723 AN, 15634548, 15634549, 15634535, 31511151

Abstract:

A plasma chamber defining an evacuated interior environment for processing a substrate includes a substrate support, an apertured gas distribution plate in spaced facing relationship to the substrate support, and adapted to flow process gases into the chamber interior environment adjacent the substrate support, the gas distribution plate and substrate support defining a substrate processing region therebetween, a hollow reentrant conduit having respective ends opening into the substrate processing region on opposite sides of the gas distribution plate, with the interior of said conduit sharing the interior environment. The conduit is adapted to accept irradiation of processing gases within the conduit to sustain a plasma in a path extending around the conduit interior and across the substrate processing region within the chamber interior environment.

US Patent:

6455431, Sep 24, 2002

Filed:

Aug 1, 2000

Appl. No.:

09/629329

Inventors:

Chang Lin Hsieh - San Jose CA
Hui Chen - Santa Clara CA
Jie Yuan - San Jose CA
Yan Ye - Saratoga CA

Assignee:

Applied Materials Inc. - Santa Clara CA

International Classification:

H01L 21302

US Classification:

438691, 438710

Abstract:

In general, the present disclosure pertains to a method for removing photoresist from locations on a semiconductor structure where its presence is undesired. In one embodiment, a method is disclosed for descumming residual photoresist material from areas where it is not desired after patterning of the photoresist. In another embodiment, a misaligned patterned photoresist is stripped from a semiconductor substrate surface. In particular, the method comprises exposing the semiconductor structure to a plasma generated from a source gas comprising NH. A substrate bias voltage is utilized in both methods in order to produce anisotropic etching. In the descumming embodiment, the critical dimensions of the patterned photoresist are maintained. In the photoresist stripping embodiment, a patterned photoresist is removed without adversely affecting a partially exposed underlying layer of an organic dielectric.

US Patent:

6458516, Oct 1, 2002

Filed:

Apr 18, 2000

Appl. No.:

09/551255

Inventors:

Yan Ye - Saratoga CA
Pavel Ionov - Sunnyvale CA
Allen Zhao - Mountain View CA
Peter Hsieh - San Jose CA
Diana Ma - Saratoga CA
Chun Yan - Santa Clara CA
Jie Yuan - San Jose CA

Assignee:

Applied Materials Inc. - Santa Clara CA

International Classification:

G03C 556

US Classification:

430317, 430313, 430311, 438703

Abstract:

A method of patterning a layer of dielectric material having a thickness greater than 1,000 , and typically a thickness greater than 5,000. The method is particularly useful for forming a high aspect ratio via or a high aspect ratio contact including self-aligned contact structures, where the aspect ratio is typically greater than 3 and the feature size of the contact is about 0. 25 m or less. In particular, an organic, polymeric-based masking material is used in a plasma etch process for transferring a desired pattern through an underlying layer of dielectric material. The combination of masking material and plasma source gas must provide the necessary high selectivity toward etching of the underlying layer of dielectric material. The selectivity is preferably greater than 3:1, where the etch rate of the dielectric material is at least 3 times greater than the etch rate of the organic, polymeric-based masking material. The dielectric material may be inorganic, for example, silicon oxide; doped silicon oxide; carbon-containing silicon oxide; SOG; BPSG; and similar materials.