Behnam M Malekkhosravi from 1024 Muirlands Vista Way, La Jolla, CA 92037, age 62

Double Data Rate System
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US Patent:

7472304, Dec 30, 2008
Filed:

Aug 30, 2006
Appl. No.:

11/517838
Inventors:

Behnam Malekkhosravi - La Jolla CA, US
Nadim Hashim Shaikli - Escondido CA, US
Assignee:

Rapid Bridge, LLC - San Diego CA
International Classification:

G06F 1/12
G06F 1/00
H03L 5/00
US Classification:

713401, 713500, 327158
Abstract:

An extendible timing architecture for an integrated circuit is disclosed. The extendible timing architecture provides metal programmable components for use with different operational clock frequencies. In some embodiments the architecture utilizes master/slave DLLs with a double data rate memory circuit.

Die Apparatus Having Configurable Input/Output And Control Method Thereof
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US Patent:

7642809, Jan 5, 2010
Filed:

Feb 6, 2007
Appl. No.:

11/672013
Inventors:

Behnam Malekkhosravi - La Jolla CA, US
Daniel J. Woodard - San Diego CA, US
David Ian West - San Diego CA, US
Assignee:

Rapid Bridge LLC - San Diego CA
International Classification:

H03K 19/0175
H03K 19/00
US Classification:

326 41, 326 47, 326101, 716 17
Abstract:

A metal configurable I/O structure for an integrated circuit is disclosed. The metal configurable I/O structure may be configured for one of any of a plurality of I/O specifications. Preferably a common voltage reference and a common current reference is generated for provision to a plurality of I/O structures.

Semiconductor Device Metal Programmable Pooling And Dies
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US Patent:

7882453, Feb 1, 2011
Filed:

Oct 17, 2007
Appl. No.:

11/874164
Inventors:

Behnam Malekkhosravi - La Jolla CA, US
David Ian West - San Diego CA, US
Assignee:

Rapid Bridge LLC - San Diego CA
International Classification:

G06F 17/50
US Classification:

716 1, 716 16, 716 17, 326 39, 257758, 714725
Abstract:

A pool of die designs includes die designs having metal programmable base layers. Die designs from the pool are selected for use in fabricating dies. Die designs are added to the pool by customization of die designs already in the pool or by preparing custom die designs that incorporate a metal programmable base layer. In some embodiments multi-tile dies are provided with I/O slots configurable for either inter tile communication or inter die communication.

Die Apparatus Having Configurable Input/Output And Control Method Thereof
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US Patent:

8072240, Dec 6, 2011
Filed:

Dec 1, 2009
Appl. No.:

12/628757
Inventors:

Behnam Malekkhosravi - La Jolla CA, US
Daniel J. Woodard - San Diego CA, US
David Ian West - San Diego CA, US
Assignee:

QUALCOMM Incorporated - San Diego CA
International Classification:

H03K 19/0175
H03K 19/00
US Classification:

326 41, 326 47, 326101
Abstract:

A metal configurable I/O structure for an integrated circuit is disclosed. The metal configurable I/O structure may be configured for one of any of a plurality of I/O specifications. Preferably a common voltage reference and a common current reference is generated for provision to a plurality of I/O structures.

Semiconductor Device Metal Programmable Pooling And Dies
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US Patent:

8392865, Mar 5, 2013
Filed:

Jan 31, 2011
Appl. No.:

13/018055
Inventors:

Behnam Malekkhosravi - La Jolla CA, US
David Ian West - San Diego CA, US
Assignee:

QUALCOMM Incorporated - San Diego CA
International Classification:

G06F 17/50
US Classification:

716128, 716129, 716130, 716131, 326 38, 326 39
Abstract:

A pool of die designs includes die designs having metal programmable base layers. Die designs from the pool are selected for use in fabricating dies. Die designs are added to the pool by customization of die designs already in the pool or by preparing custom die designs that incorporate a metal programmable base layer. In some embodiments multi-tile dies are provided with I/O slots configurable for either inter tile communication or inter die communication.

Method And Architecture For Integrated Circuit Design And Manufacture
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US Patent:

20050193353, Sep 1, 2005
Filed:

Feb 27, 2004
Appl. No.:

10/789066
Inventors:

Behnam Malekkhosravi - La Jolla CA, US
Daniel Woodard - San Diego CA, US
International Classification:

G06F017/50
US Classification:

716001000
Abstract:

A system for integrated circuit (IC) design. A structural multi-project wafer (SMPW) comprises a plurality of pre-manufactured and pre-validated functional blocks. The SMPW is pre-fabricated up to a contact layer so that a user can customize and program different blocks of the SMPW to the user's requirements. An SMPW provider maintains an inventory of SMPWs. If one of the SMPWs can meet all of a user's IC design requirements, or can serve an intermediate step in a user's IC design process, such as market/concept validation or IP validation, the SMPW is provided to the user. The user can then proceed directly to production using a streamlined design flow having a very short cycle time of 1-3 months. Otherwise, the user proceeds to production using a normal design flow having a much longer cycle time.

Behnam M Malekkhosravi