Abhaya J Asthana

US Patent:

20070190996, Aug 16, 2007

Filed:

Feb 15, 2006

Appl. No.:

11/354709

Inventors:

Abhaya Asthana - Framingham MA, US
Eric Bauer - Freehold NJ, US
Peter Bosch - New Providence NJ, US
Xuemei Zhang - Morganville NJ, US

International Classification:

H04M 3/00

US Classification:

455420000, 455423000

Abstract:

The invention includes a method and apparatus for reconfiguring a first base station element to attempt to serve at least a portion of the plurality of wireless terminals served by a second base station element in response to detection of a failure condition at a second base station element that was serving the plurality of wireless terminals prior to the occurrence of the failure condition.

US Patent:

20070226546, Sep 27, 2007

Filed:

Dec 22, 2005

Appl. No.:

11/315772

Inventors:

Abhaya Asthana - Framingham MA, US
Eric Bauer - Freehold NJ, US
Xuemei Zhang - Morganville NJ, US

International Classification:

G06F 11/00

US Classification:

714047000

Abstract:

The invention includes a method for determining a software reliability metric, including obtaining testing defect data, obtaining test case data, determining testing exposure time data using the test case data, and computing the software reliability metric using testing defect data and testing exposure time data. The defect data includes software defect records. The test case data includes test case execution time data. A testing results profile is determined using testing defect data and testing exposure time data. A software reliability model is selected according to the testing results profile. A testing defect rate and a number of residual defects are determined by using the software reliability model and the testing results profile. A testing software failure rate is determined using the testing defect rate and the number of residual defects. A field software availability metric is determined using the field software failure rate determined using the testing software failure rate.

US Patent:

20130097304, Apr 18, 2013

Filed:

Oct 14, 2011

Appl. No.:

13/273415

Inventors:

Abhaya ASTHANA - Framingham MA, US
Marc S. Benowitz - Hillsborough NJ, US
Uma Chandrashekhar - Morganville NJ, US

International Classification:

G06F 15/173

US Classification:

709224, 709226

Abstract:

A dynamic reliability and security capability is provided. The dynamic reliability and security capability may be configured to support use of a dynamic reliability profile (DRP) that specifies the reliability parameters of a customer both as function of time and as a function of the requirements of the application or service of the customer. The reliability parameters may specify reliability requirements and/or goals of the customer, thereby providing a time varying requirements/goals profile. The dynamic reliability and security capability may be configured to dynamically configure the cloud resources to provide the required reliability as specified by the DRP. The RSG capability may be configured to subsequently monitor and meter the behavior to assure that the specified reliability is in fact being delivered, which may include use of self-healing capabilities to provide service assurance.

US Patent:

55903703, Dec 31, 1996

Filed:

Nov 16, 1995

Appl. No.:

8/558208

Inventors:

Abhaya Asthana - Berkeley Heights NJ
Mark R. Cravatts - Berkeley Heights NJ
Paul Krzyzanowski - Fanwood NJ

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

G06F 1200

US Classification:

395800

Abstract:

A memory system contains one or more active storage elements. Each active storage element includes a memory element and a processing element associated with the memory element. The memory element contains microcode for implementing a specific function. A first bus connects the processing element to a host processor. A second bus connects the processing element to a peripheral.

US Patent:

40619044, Dec 6, 1977

Filed:

Mar 3, 1976

Appl. No.:

5/663297

Inventors:

George Hannauer - E. Windsor NJ
Abhaya Asthana - Long Branch NJ

Assignee:

Electronic Associates, Inc. - Long Branch NJ

International Classification:

G06J 100
G06G 728

US Classification:

364608

Abstract:

A variable analog function generator which is independent of an external computer during the time that it generates at least one predetermined output function of at least one input variable. The output function is expressed in terms of hybrid variables each having an analog portion and a digital portion. The function generator has a first dedicated memory which is loaded during set up time with data related to breakpoints defining the input variable. A second dedicated memory is loaded during set up time with tables of values defining the digital portion. During function generation, the analog portions are generated in response to (1) the input variable and (2) the data related to the breakpoints which is accessed in parallel from the first dedicated memory. The output function is generated in response to (1) the analog portions and (2) the tables of values accessed from the second dedicated memory.

US Patent:

57403848, Apr 14, 1998

Filed:

Feb 16, 1996

Appl. No.:

8/603022

Inventors:

Abhaya Asthana - Berkeley Heights NJ
Venkatesh Krishnaswamy - Highland Park NJ

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

G06F 1336
G06F 1300

US Classification:

395306

Abstract:

A multimedia system includes a plurality of components. Each component has a set of hardware resources which are used to perform basic functions. Each component further contains knowledge regarding the properties, limitations and behavior of the resources. A backplane receives each of the components. The backplane includes a plurality of programmable interfaces. Each interface interfaces with a different component. A control thread is associated with each component which manages the resources contained in the component. The combination of the backplane, control thread and component form a basic service which operates independently from other basic services created by the system.

US Patent:

40577112, Nov 8, 1977

Filed:

Mar 17, 1976

Appl. No.:

5/667960

Inventors:

Abhaya Asthana - Long Branch NJ
George Hannauer - E. Windsor NJ

Assignee:

Electronic Associates, Inc. - Long Branch NJ

International Classification:

G06J 100

US Classification:

364600

Abstract:

An analog switching system having fan-out for switching a plurality of inputs coupled to analog signal sources with respect to a plurality of outputs coupled to analog signal destinations. A three stage switch matrix includes input, middle and output switch blocks with each block having a plurality of analog switch means and latching means. Any one input terminal of a switch block may be connected to any one or more of the output terminals of that block. A matrix controller coupled to each of the switch blocks addresses each switch block and actuates at least one of the latching means to provide a connection assignment for at least one of the analog switching means.

US Patent:

51347113, Jul 28, 1992

Filed:

May 13, 1988

Appl. No.:

7/193987

Inventors:

Abhaya Asthana - Berkeley Heights NJ
Jonathan A. Chandross - Murray Hill NJ
Hosagrahar V. Jagadish - Berkeley Heights NJ
Scott C. Knauer - Mountainside NJ
Daniel Lin - Berkeley Heights NJ

Assignee:

AT&T Bell Laboratories - Murray Hill NJ

International Classification:

G06F 1300

US Classification:

395800

Abstract:

A programmable memory system that interfaces with a computer's control and data manipulation units, and is capable of performing the manipulation, bookkeeping, and checking that would normally be performed by the computer. The memory system comprises active structure modules that are interconnected in a network to form clusters. The clusters are interconnected to form an aggregate memory system. Each ASE contains a processor section and a conventional memory section.