Adrian J Murphy

US Patent:

52276635, Jul 13, 1993

Filed:

Mar 18, 1992

Appl. No.:

7/855118

Inventors:

Sadanand Patil - San Jose CA
Adrian Murphy - San Jose CA
Keith Newman - Sunnyvale CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 3902
H01L 2302
H01L 2348
H02B 100

US Classification:

257718

Abstract:

A metallic or ceramic dam structure surrounding a semiconductor die in a semiconductor device assembly is disclosed. The dam structure forms a cavity containing a potting compound encapsulating the die. The dam structure may also be provided with a flat lid portion, enclosing the cavity and forming a flat, exterior, heat-dissipating surface for the semiconductor device assembly. Further, an additional add-on structure, having heat dissipating fins, may be joined to the dam structure, exterior the semiconductor device assembly, to provide additional heat dissipation. The add-on structure is particularly well-suited to applications where air cooling is available.

US Patent:

51737663, Dec 22, 1992

Filed:

Jun 25, 1990

Appl. No.:

7/543989

Inventors:

Jon M. Long - Livermore CA
Rachel S. Sidorovsky - San Jose CA
Michael J. Steidl - San Jose CA
Adrian Murphy - San Jose CA
Bidyut Sen - Milpitas CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H05K 118

US Classification:

257687

Abstract:

A semiconductor device package and a method of making such a package is described. The package comprises a flexible packaging substrate having a patterned metal layer onto which a semiconductor die is attached and a patterned insulative layer attached to the metal layer. The insulative layer includes an annular epoxy-seal gap. A glob of silicone gel is deposited and cured on the die. A casting frame is connected to the metal layer of the flexible substrate on the same side as the die. A backside moisture-blocking layer of material is attached to an opposed side of the tape. The frame and the backside layer are attached to the metal layer of the flexible substrate using cross-linkable epoxy adhesives. These epoxy adhesives join through the epoxy-seal gap to define an epoxy-seal around the die. A thermoset type of molding compound is then poured into the casting frame to define a moisture resistant package body.

US Patent:

54472296, Sep 5, 1995

Filed:

Jun 28, 1993

Appl. No.:

8/085260

Inventors:

Brian Lynch - Milpitas CA
Patrick O'Brien - Palo Alto CA
Adrian Murphy - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

B65D 8542

US Classification:

206706

Abstract:

Industry-standard COT/TAB integrated circuit part carrier frame members are receivable into a shipping tube member in a stack which rests at one end on paired retaining pins and at the other end is retained by a closure member of the shipping tube. As so disposed in the shipping tube, the carrier frames are securely held with virtually no risk that they will slip out of place within the shipping tube. The shipping tube member includes side walls which define plural pairs of apertures spaced along the length of the shipping tube so that: the paired pins may be relocated to adapt the shipping tube to various shipment sizes. The remainder of the shipping tube remains empty to reduce both the cost of carrier frames conventionally used just as filler, as well as reducing shipping costs by eliminating the weight of these filler carrier frames which are shipped empty.

US Patent:

59922427, Nov 30, 1999

Filed:

May 4, 1998

Appl. No.:

9/072915

Inventors:

Adrian Murphy - San Jose CA
Manickam Thavarajah - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G01N 300

US Classification:

73840

Abstract:

An Integrated Circuit (IC) wafer test fixture includes a baseplate and a top plate. During testing, an IC wafer is positioned between the baseplate and top plate with annular rubber gaskets, forming sealed cavities above and below the IC wafer. A fluid pressure generator with a pressure gauge inserts a fluid under pressure into one of the cavities, causing the IC wafer to be subject to stress. The fluid distributes a uniform pressure load on the surface of the IC wafer. The pressure of the fluid may be gradually increased until a desired pressure is obtained or the wafer fails. The pressure at failure is recorded, and by calculation the failure stress of the IC wafer can be determined. A second embodiment of the test fixture includes a pressure vessel with a threaded sealed opening at the top and a stepped sealed opening at the bottom. The inner diameter of the insert is sized for an IC wafer.

US Patent:

61176958, Sep 12, 2000

Filed:

May 8, 1998

Appl. No.:

9/075300

Inventors:

Adrian S. Murphy - San Jose CA
Manickam Thavarajah - San Jose CA
Patrick J. Variot - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2144

US Classification:

438 15

Abstract:

An apparatus and method are presented for testing an adhesive layer formed between an integrated circuit and a plate, wherein the plate may be semiconductor device package substrate or a heat spreader. The apparatus includes a pull stud and a pull arm. The pull stud has an upper portion and a lower portion, wherein the lower portion is attached to a surface of the integrated circuit opposite the plate. The upper portion of the pull stud may be, for example, a tapered cylinder having a large end and a small end. The small end meets the lower portion of the pull stud. The pull arm has two opposed ends and at least one bracket for receiving a force. One of the pull arm ends has a "V"-shaped opening surrounded by a lip which receives the upper portion of the pull stud. During use, the lip contacts and retains the upper portion of the pull stud. The opening has an upper wall, and an upper surface of the pull stud contacts the upper wall when the upper portion of the pull stud is inserted into the opening.