Ahmet Ahmet Tura

US Patent:

20190164809, May 30, 2019

Filed:

Dec 29, 2017

Appl. No.:

15/859323

Inventors:

- Santa Clara CA, US
Ahmet TURA - Portland OR, US
Byron HO - Hillsboro OR, US
Subhash JOSHI - Hillsboro OR, US
Michael L. HATTENDORF - Portland OR, US
Christopher P. AUTH - Portland OR, US

International Classification:

H01L 21/762
H01L 29/78
H01L 21/8234
H01L 21/8238
H01L 21/311
H01L 29/08
H01L 27/11
H01L 29/66
H01L 21/308
H01L 27/092
H01L 29/51
H01L 21/285
H01L 21/28
H01L 21/033
H01L 21/768
H01L 23/532
H01L 23/522
H01L 23/528
H01L 49/02

Abstract:

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An insulating structure is directly adjacent sidewalls of the lower fin portion of the fin. A first gate electrode is over the upper fin portion and over a first portion of the insulating structure. A second gate electrode is over the upper fin portion and over a second portion of the insulating structure. A first dielectric spacer is along a sidewall of the first gate electrode. A second dielectric spacer is along a sidewall of the second gate electrode, the second dielectric spacer continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode.