Alan J Schiffleger

US Patent:

53718798, Dec 6, 1994

Filed:

Apr 26, 1994

Appl. No.:

8/233222

Inventors:

Alan J. Schiffleger - Chippewa Falls WI

Assignee:

Cray Research, Inc. - Eagan MN

International Classification:

G06F 9455

US Classification:

395500

Abstract:

A method of implementing a privileged instruction that enables the development of new operating systems in user mode. The instruction decode logic includes a maskable interrupt generator that interrupts the processor during the processing of privileged instructions in user mode. An exception handler processes the privileged instruction interrupt and performs a function similar to the execution of the privileged instruction in privileged instruction mode. The combination of the privileged instruction interrupt and the post-interrupt exception handling enables the operating system developer to test new operating systems by laying them over the current operating system.

US Patent:

52476375, Sep 21, 1993

Filed:

Jun 1, 1990

Appl. No.:

7/531861

Inventors:

George W. Leedom - Jim Falls WI
Alan J. Schiffleger - Chippewa Falls WI
Ram K. Gupta - Eau Claire WI

Assignee:

Cray Research, Inc. - Eagan MN

International Classification:

G06F 1314

US Classification:

395425

Abstract:

The present invention provides a memory interface system wherein there is provided a memory having multiple ports and divided into sections, with each section divided into subsections, with memory banks within each subsection, and the banks divided into at least two bank groups. The invention further provided a memory interface for controlling the referencing of said memory banks according to which bank group they are in.

US Patent:

60981628, Aug 1, 2000

Filed:

Aug 24, 1998

Appl. No.:

9/138613

Inventors:

Alan J. Schiffleger - Chippewa Falls WI
Ram K. Gupta - Eau Claire WI
Christopher C. Hsiung - Eau Claire WI

Assignee:

Cray Research, Inc. - Eagan MN

International Classification:

G06F 915

US Classification:

712 4

Abstract:

Vector shifting elements of a vector register by varying amounts in a single process is achieved in a vector supercomputer processor. A first vector register contains a set of operands, and a second vector register contains a set of shift counts, one shift count for each operand. Operands and shift counts are successively transferred to a vector shift functional unit, which shifts the operand by an amount equal to the value of the shift count. The shifted operands are stored in a third vector register. The vector shift functional unit also achieves word shifting of a predetermined number of vector register elements to different word locations of another vector register.

US Patent:

54349702, Jul 18, 1995

Filed:

Feb 14, 1991

Appl. No.:

7/655296

Inventors:

Alan J. Schiffleger - Chippewa Falls WI

Assignee:

Cray Research, Inc. - Eagan MN

International Classification:

G06F 1516

US Classification:

395200

Abstract:

A tightly coupled interprocessor communication system based on a common shared resource circuit and adapted particularly to a multiprocessing system including 2. sup. N processors. A local control circuit is connected to each processor and a shared resource circuit is tightly coupled through the local control circuits to each processor. The shared resource circuit includes a shared semaphore register, a shared information register and a read and increment circuit which can be used to increment the contents of a shared information register as a single instruction. The local control circuit includes an issue control circuit used to determine when a transaction with the shared resource circuit is permitted, a circuit which generates a command to the shared resource circuit when the transaction is permitted and a real time clock.

US Patent:

54817463, Jan 2, 1996

Filed:

Mar 29, 1994

Appl. No.:

8/218997

Inventors:

Alan J. Schiffleger - Chippewa Falls WI
Ram K. Gupta - Eau Claire WI
Christopher C. Hsiung - Eau Claire WI

Assignee:

Cray Research, Inc. - Eagan MN

International Classification:

G06F 9315
G06F 9302
G06F 930

US Classification:

395800

Abstract:

Vector shifting elements of a vector register by varying amounts in a single process is achieved in a vector supercomputer processor. A first vector register contains a set of operands, and a second vector register contains a set of shift counts, one shift count for each operand. Operands and shift counts are successively transferred to a vector shift functional unit, which shifts the operand by an amount equal to the value of the shift count. The shifted operands are stored in a third vector register. The vector shift functional unit also achieves word shifting of a predetermined number of vector register elements to different word locations of another vector register.

US Patent:

55264875, Jun 11, 1996

Filed:

Feb 9, 1989

Appl. No.:

7/308401

Inventors:

Alan J. Schiffleger - Chippewa Falls WI

Assignee:

Cray Research, Inc. - Eagan MN

International Classification:

G06F 15163

US Classification:

395821

Abstract:

A system for interprocessor communication including a shared register resource accessible by any one of the processors through the using internal communication paths. The shared register resource is distributed among the processors with each processor including a portion of the total system resource. Each processor includes an access circuit for receiving instructions from the CPU and generating control bytes to be distributed to the shared register resource circuits in each of the processors, which use the control byte to control shared resource access. Each shared register resource circuit is capable of controlling the I/O channels associated with its respective processor. A local access circuit for each CPU is capable of obtaining access to and controlling any of the I/O channels in the system via the shared register resource circuits.

US Patent:

46369422, Jan 13, 1987

Filed:

Apr 25, 1983

Appl. No.:

6/488082

Inventors:

Steve S. Chen - Chippewa Falls WI
Alan J. Schiffleger - Chippewa Falls WI
Eugene R. Somdahl - St. Paul MN
Lee Higbie - Arlington Heights IL

Assignee:

Cray Research, Inc. - Chippewa Falls WI

International Classification:

G06F 1300

US Classification:

364200

Abstract:

A multiprocessing system and method for multiprocessing is disclosed. A pair of processors are provided, and each are connected to a central memory through a plurality of memory reference ports. The processors are further each connected to the plurality of shared registers which may be directly addressed by either processor at rates commensurate with intraprocessor operation. The shared registers include registers for holding scalar and address information and registers for holding information to be used in coordinating the transfer of information through the shared registers. A multiport memory is provided and includes a conflict resolution circuit which senses and prioritizes conflicting references to the central memory. Each CPU is interfaced with the central memory through three ports, with each of the ports handling different ones of several different types of memory references which may be made. At least one I/O port is provided to be shared by the processors in transferring information between the central memory and peripheral storage devices.

US Patent:

46619003, Apr 28, 1987

Filed:

Apr 30, 1986

Appl. No.:

6/858862

Inventors:

Steve S. Chen - Chippewa Falls WI
Alan J. Schiffleger - Chippewa Falls WI

Assignee:

Cray Research, Inc. - Minneapolis MN

International Classification:

G06F 15347

US Classification:

364200

Abstract:

A pair of processors are each connected to a central memory through a plurality of memory reference ports. The processors are further each connected to a plurality of shared registers which may be directly addressed by either processor at rates commensurate with intra-processor operation. The shared registers include registers for holding scalar and address information and registers for holding information to be used in coordinating the transfer of information through the shared registers. A multiport memory is provided and includes a conflict resolution circuit which senses and prioritizes conflicting references to the central memory. Each CPU is interfaced with the central memory through three ports, with each of the ports handling different ones of several different types of memory references which may be made. At least one I/O port is provided to be shared by the processors in transferring information between the central memory and peripheral storage devices. A vector register design is also disclosed for use in vector processing computers, and provides that each register consist of at least two independently addressable memories, to deliver data to or accept data from a functional unit.