Allegra R Segura

US Patent:

8010838, Aug 30, 2011

Filed:

Nov 20, 2008

Appl. No.:

12/274434

Inventors:

Sheldon Ray Bailey - Rochester MN, US
Bradley W. Bishop - Rochester MN, US
Alongkorn Kitamorn - Austin TX, US
Erlander Lo - Austin TX, US
Allegra R. Segura - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00

US Classification:

714 10

Abstract:

Disclosed is a computer implemented method, data processing system, and apparatus to respond to detection of a hardware interface error on a system bus, for example, during a concurrent maintenance operation. The service processor may receive an error on the system bus. The error identifies at least one field replaceable unit and may inhibit the suppression of clock signal to the field replaceable unit. The service processor adds an identifier of the field replaceable unit to an eligible Field Replaceable Unit (FRU) list. The service processor recursively adds at least one field replaceable unit that the field replaceable unit depends upon. The service processor suppresses the clock signal to the field replaceable unit. The service processor inhibits tagging the field replaceable unit as unusable for next initial program load.

US Patent:

20080141010, Jun 12, 2008

Filed:

Dec 12, 2006

Appl. No.:

11/609427

Inventors:

Daniel M. Crowell - Rochester MN, US
Philip J. Sanders - Rochester MN, US
Allegra R. Segura - Austin TX, US

International Classification:

G06F 11/30

US Classification:

712226, 712E09059

Abstract:

According to a method of data processing in a data processing system, a hardware management component receives from a software component of the data processing system a request for management access to a hardware component of the data processing system. In response to receipt of the request for management access, the hardware management component determines whether or not the request contains a parameter indicative of the intended scope of hardware components to be accessed in response to the request. In response to the request, the hardware management component selects a scope in accordance with the determination and issues one or more hardware management commands to one or more target hardware components of the data processing system within the selected scope, such that an operating state of the one or more target hardware components is modified.