Aloysius T Tam from 990 Azalea Dr, Sunnyvale, CA 94086

Tag Buffer With Testing Capability
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US Patent:

47409711, Apr 26, 1988
Filed:

Feb 28, 1986
Appl. No.:

6/835078
Inventors:

Aloysius T. Tam - Sunnyvale CA
Thomas S. Wong - San Jose CA
Jim L. Michelsen - Santa Clara CA
David F. Naren - Cupertino CA
David Wang - Palo Alto CA
Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:

G11C 2900
G01R 3128
US Classification:

371 21
Abstract:

A tag buffer having built-in testing capabilities is disclosed. In a single-chip, integrated-circuit design which includes a SRAM, a parity generator and checker, and a comparator, a method and capability of testing the functionality of the SRAM and parity components is defined. For an embodiment in which the SRAM component includes a redundancy scheme for replacing a defective memory array row, a test for determining whether a redundant row has been used is also provided.

Digital Memory With Reset/Preset Capabilities
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US Patent:

48051497, Feb 14, 1989
Filed:

Aug 28, 1986
Appl. No.:

6/901914
Inventors:

Aloysius Tam - Sunnyvale CA
Thomas S. Wong - San Jose CA
David Wang - Berkeley CA
David Naren - Cupertino CA
Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:

G11C 1140
US Classification:

365155
Abstract:

A digital memory characterized by a plurality of memory cells arranged into a matrix having rows and columns; a row activation circuit for concurrently activating all of the rows of the matrix; and column activation means for concurrently applying either a reset signal or a preset signal to the columns of the matrix. The column activation circuit can include a plurality of digital switches coupled to reset and preset lines associated with each column of the matrix; and reset/preset logic which control the digital switches to selectively couple the reset and preset lines to a constant current source. A complementary, multi-emitter flip-flop memory cell is formed on a semiconductor substrate and includes "riser" portions.

Random Access Memory Device With Block Reset
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US Patent:

47899670, Dec 6, 1988
Filed:

Sep 16, 1986
Appl. No.:

6/908072
Inventors:

May-Lin Lee - Cupertino CA
Moon S. Kok - Milpitas CA
James Yu - San Jose CA
Aloysius T. Tam - Sunnyvale CA
Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:

G11C 700
US Classification:

365189
Abstract:

An apparatus for storing data for read and write access receiving reset control signals, comprising a plurality of storage blocks, each block including an array of memory units for storing a unit of data is provided that is reset along storage block boundaries. A reset control means, coupled to receive the reset control signals which identify at least one of the storage blocks, is included for generating block reset signals. A means, coupled to the memory units in each storage block and to receive the block reset signals, for resetting the identified block of memory to 0. .

Memory With Sequential Mode
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US Patent:

46807381, Jul 14, 1987
Filed:

Jul 30, 1985
Appl. No.:

6/760712
Inventors:

Aloysius T. Tam - Sunnyvale CA
Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:

G11C 800
US Classification:

365239
Abstract:

A memory comprising a plurality of memory cells, a column decoder, a row decoder, a plurality of shift registers and a multiplexer is provided for addressing the memory cells in a conventional manner or in a high-speed sequential mode. In the sequential mode alternate cells from each of two sets of cells are addressed and their contents provided on a data output line, or data presented to them on a data input line, at a system clock rate which is much faster than the conventional mode.

Integrated Electronic Memory Circuit With Internal Timing And Operable In Both Latch-Based And Register-Based Systems
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US Patent:

48254169, Apr 25, 1989
Filed:

May 7, 1986
Appl. No.:

6/860727
Inventors:

Aloysius T. Tam - Sunnyvale CA
N. Bruce Threewitt - Fremont CA
Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:

G11C 700
G11C 800
US Classification:

365194
Abstract:

An integrated electronic memory circuit is provided which includes memory circuitry for storing binary data in an array of memory locations; first data signal providing circuitry for providing input data signals to the memory circuitry, for storage by the memory circuitry as binary data at respective memory locations; and write signal generator circuitry for generating a write signal causing the memory circuitry to accept input data signals from the first data signal providing circuitry for storing in the array.

Aloysius T Tam