Search

Ananth S Vijalapuram

age ~67

from Plano, TX

Also known as:
  • Ananth S Vijalapur
  • Ananth Sayan
  • Ana Vijalapuram
  • Sayan V Ananth
  • N M
  • Ananth M
  • Ananth A
Phone and address:
5401 Independence Pkwy, Plano, TX 75023
9729648457

Ananth Vijalapuram Phones & Addresses

  • 5401 Independence Pkwy, Plano, TX 75023 • 9729648457
  • 7100 Bending Oak Rd, Austin, TX 78749 • 5123014762
  • 5417 Mo Pac Cir, Austin, TX 78749 • 5128999037
  • Dallas, TX
  • Tempe, AZ
  • Sherman, TX
  • Randolph, NJ

Us Patents

  • Method And Apparatus Facilitating Insertion And Removal Of Modules In A Computer System

    view source
  • US Patent:
    6564279, May 13, 2003
  • Filed:
    Sep 29, 1999
  • Appl. No.:
    09/408735
  • Inventors:
    Patrick C. Neil - Richardson TX
    Robert Craig Hugus - Sherman TX
    Ananth S. Vijalapuram - Plano TX
  • Assignee:
    Texas Instruments Incorporated - Dallas TX
  • International Classification:
    G06F 1300
  • US Classification:
    710302, 713322, 713501, 713600
  • Abstract:
    A computer system ( ) includes a plurality of hot-plug sockets ( ), each of which can be selectively uncoupled from a bus ( ) during normal system operation, in order to facilitate insertion or removal of module ( ). A clock signal (PCLK) is generated at one of two different frequencies, and at system power-up a clock arbitration circuit ( ) is responsive to modules which are present for specifying a speed of the clock signal. A hot-plug controller circuit ( ) can selectively uncouple one of the hot-plug sockets from the bus during normal operation to facilitate insertion or removal of a module, and also facilitates a determination of whether clock speed requirements of an inserted module are compatible with the current clock speed. The selected socket is recoupled to the bus only if the inserted module is compatible with the current clock speed.

Resumes

Ananth Vijalapuram Photo 1

Senior Design Verification Engineer

view source
Location:
Austin, TX
Industry:
Semiconductors
Work:
Intel Corporation
Senior Design Verification Engineer

Marvell Semiconductor Oct 2010 - Aug 2015
Design Verification Manager

Marvell Semiconductor Nov 2006 - Oct 2010
Verification Engineer

Intel Corporation 2004 - 2006
Verification Engineer

Ess Technology, Inc. 2001 - 2003
Senior Design Verification Engineer
Education:
The University of Texas at Dallas 1997 - 1999
Master of Science, Masters, Electrical Engineering
University of Mysore 1984 - 1986
Masters, Master of Technology, Electronics
University of Mysore 1975 - 1980
Bachelor of Engineering, Bachelors, Electronics, Engineering, Communications
Skills:
Functional Verification
Asic
Soc
Verilog
Systemverilog
Processors
Simulations
Vhdl
Modelsim
Vlsi
Management
Debugging
Low Power Design
Application Specific Integrated Circuits
Arm
Semiconductors
Networking Skills
Logic Design
Mixed Signal
Vmm
Ic
Amba Ahb
System on A Chip
Integrated Circuits
Cmos
Fpga
Hardware Architecture
Digital Signal Processors
Microarchitecture
Tcl
Eda
Cadence
Microprocessors
Power Management
Integrated Circuit Design
Computer Architecture
Interests:
Science and Technology
Education
Environment
Health
Languages:
Hindi
Telugu
Kannada
Tamil
Marathi
English
Ananth Vijalapuram Photo 2

Design Verification Engineer

view source
Location:
Austin, TX
Industry:
Consumer Electronics
Work:
Marvell Semiconductor
Design Verification Engineer
Ananth Vijalapuram Photo 3

Ananth S Vijalapuram

view source

Facebook

Ananth Vijalapuram Photo 4

Ananth Vijalapuram

view source

Get Report for Ananth S Vijalapuram from Plano, TX, age ~67
Control profile