Bennett A Joiner

US Patent:

6847102, Jan 25, 2005

Filed:

Nov 8, 2002

Appl. No.:

10/290959

Inventors:

Mark A. Gerber - Austin TX, US
Bennett A. Joiner - Austin TX, US
Jose Antonio Montes De Oca - New Braunfels TX, US
Trent A. Thompson - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 23495

US Classification:

257668, 257687

Abstract:

A package substrate () has a first surface, a second surface opposite a first surface, and a cavity () formed in the first surface that extends into the package substrate. The cavity has a cavity wall substantially perpendicular to the first and second surfaces. An integrated circuit die () is placed in the cavity, and a conductive material () is placed in the cavity to thermally couple an outer wall of the integrated circuit to the cavity wall. The conductive material improves the heat dissipation path between the integrated circuit die and the package substrate. The cavity may extend through the package substrate to the second surface such that the second surface of the package substrate is substantially coplanar to a surface of the integrated circuit die. An encapsulation layer () may be formed over the conductive material, integrated circuit die, and at least a portion of the first surface of the package substrate.

US Patent:

6933599, Aug 23, 2005

Filed:

Oct 27, 2003

Appl. No.:

10/694146

Inventors:

Bennett A. Joiner - Austin TX, US
Yaping Zhou - Austin TX, US
Ben W. Herberg - Pflugerville TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L023/48

US Classification:

257690, 257691, 257693, 257773, 257659, 257786, 257784, 257777, 257775, 257776, 257723, 257676, 257774, 257737, 257734, 257728, 439108

Abstract:

A semiconductor device has a die () overlying and electrically connected to a support structure (), such as a substrate or a lead frame, via a plurality of interconnects. Aggressor interconnects () are noise sources to victim interconnects () carrying sensitive signals. An arrangement of shield interconnects () surround the victim interconnect () in a cage-like structure to significantly block noise from the aggressor interconnect. In one form the shield interconnects are ground or power supply and the victim interconnect may be, for example, a clock signal or an RF signal. The number of shield interconnects and the number of protected victim interconnects varies depending upon design requirements. Either wire bonding or other interconnect technology (e. g. bump) is applicable.

US Patent:

7361985, Apr 22, 2008

Filed:

Oct 27, 2004

Appl. No.:

10/974658

Inventors:

Yuan Yuan - Austin TX, US
Bennett Joiner - Austin TX, US
Chuchung (Stephen) Lee - Round Rock TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 23/34

US Classification:

257713, 257E23083

Abstract:

An integrated circuit package () is provided which comprises a substrate (), an integrated circuit () mounted on the substrate, and a compressive, thermally conductive interposer () mounted on the integrated circuit.

US Patent:

57342016, Mar 31, 1998

Filed:

Oct 21, 1994

Appl. No.:

8/328978

Inventors:

Frank Djennas - Austin TX
Wilhelm Sterlin - Austin TX
Bennett A. Joiner - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2348

US Classification:

257783

Abstract:

A low profile semiconductor device (24) is manufactured by mounting a semiconductor die (26) onto a substrate (28) using an interposer (30). The interposer couples an active surface (32) of the die (26) to conductive traces (33) on the top surface of the substrate. The interposer is directionally conductive so that electrical conductivity is limited to the z-direction through thickness of the interposer. The interposer both affixes the die to the substrate and provides the first level of interconnects for the device. The inactive surface (36) of the die can be exposed for efficient thermal dissipation. An optional heat spreader (50) may be added for increased thermal management. The device may be overmolded, glob-topped, capped, or unencapsulated. Separate die-attach and wire bonding processes are eliminated. A second level of interconnects are provided by either solder balls (38), solder columns (44), or pins (64).

US Patent:

51478218, Sep 15, 1992

Filed:

Oct 31, 1991

Appl. No.:

7/786205

Inventors:

Michael B. McShane - Austin TX
James J. Casto - Austin TX
Bennett A. Joiner - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2156
H01L 2158
H01L 2160
H01L 21603

US Classification:

437212

Abstract:

A method for making a semiconductor device having a heat sink is provided in which an opening through the heat sink enables a vacuum source to be applied to a semiconductor die mounting surface. In one form, a semiconductor die is attached to a mounting surface of a leadframe. The leadframe also has a plurality of leads which are electrically coupled to the semiconductor die. The semiconductor die and portions of the leads are encapsulated in a package body. Also incorporated into the package body is a heat sink. The heat sink has an opening which extends through the heat sink and exposes a portion of the mounting surface of the leadframe. The opening is used to apply a vacuum to the mounting surface during the formation of the package body so that the mounting surface and heat sink are held in close proximity. The closeness provides a good thermal conduction path from the semiconductor die to the ambient, thereby enhancing the thermal dissipation properties of the device.

US Patent:

56839448, Nov 4, 1997

Filed:

Sep 1, 1995

Appl. No.:

8/522889

Inventors:

Bennett A. Joiner - Austin TX
Greg L. Ridsdale - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2158
H01L 2160

US Classification:

437220

Abstract:

The device has a semiconductor die (18) mounted upon a downset X-shape die support (12) of a lead frame (10, 40). The lead frame also has tie bars (16) which are connected to the X-shape die support. Attached to the tie bars are thermal bars (14, 14') which are located between the semiconductor die and inner portion of the leads (20). The inner portion of the leads, the tie bars, and the thermal bars are offset from the plane occupied by the X-shape die support. The thermal bars aid in dissipating the heat from the die into the nearby lead tips so that the heat can be conducted out of the package body (30) through the thermally conductive lead frame. The semiconductor die is wire bonded to the inner portion of the leads. A package body (30) protects the die, the wire bonds (26), the thermal bars, and the inner portion of the leads.

US Patent:

51052598, Apr 14, 1992

Filed:

Sep 28, 1990

Appl. No.:

7/589465

Inventors:

Michael B. McShane - Austin TX
James J. Casto - Austin TX
Bennett A. Joiner - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2328

US Classification:

357 72

Abstract:

A semiconductor device having a heat sink is provided in which an opening through the heat sink enables a vacuum source to be applied to a semiconductor die mounted surface. In one form, a semiconductor die is attached to a mounting surface of a leadframe. The leadframe also has a plurality of leads which are electrically coupled to the semiconductor die. The semiconductor die and portions of the leads encapsulated in a package body. Also incorporated in the package body is a heat sink. The heat sink has an opening which extends through the heat sink and exposes a portion of the mounting surface of the leadframe. The opening is used to apply a vacuum to the mounting surface during the formation of the package body so that the mounting surface and heat sink are held in close proximity. The closeness provides a good thermal conduction path from the semiconductor die to the ambient, thereby enhancing the thermal dissipation properties of the device.

US Patent:

54830982, Jan 9, 1996

Filed:

Oct 18, 1994

Appl. No.:

8/326160

Inventors:

Bennett A. Joiner - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 23495

US Classification:

257676

Abstract:

A molded semiconductor device (24) having greater resistance to package cracking during board mounting in addition to increased thermal performance is provided wherein the device has a reduced semiconductor die to flag interface and a drop-in heat sink. The semiconductor die (12) is mounted on a leadframe (16) having a flag (15) with an opening to expose a substantial portion of the inactive surface (14) of the die (12). Decreasing the interfacial contact area between the die (12) and the flag (15) reduces the risk of package cracking during board mounting by limiting the area where delamination typically occurs. An encapsulant (22) forms a package body which encompasses an opening (23) to expose a substantial portion of the inactive surface (14) of the semiconductor die (12). A heat sink (26) is inserted into the opening (23), directly coupling the heat sink (26) to the die (12), after the semiconductor package is mounted onto a printed circuit board.