Brian F Bernier

US Patent:

7509250, Mar 24, 2009

Filed:

Nov 4, 2005

Appl. No.:

11/266889

Inventors:

Edwin D. Cruzado - Plant City FL, US
William J. Dalzell - Parrish FL, US
Brian R. Bernier - Tampa FL, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G06F 9/455

US Classification:

703 28, 713193, 713165, 713173, 713189, 380 28, 380 30, 380 43, 726 23, 726 4, 726 27, 702106, 702 35

Abstract:

In one embodiment, a system comprises debug functionality, a debug interface communicatively coupled to the debug functionality, and a hardware key interface. Communication with the debug functionality over the debug interface is not permitted if an authorized hardware key is not communicatively coupled to the hardware key interface.

US Patent:

7844997, Nov 30, 2010

Filed:

Jan 12, 2006

Appl. No.:

11/330790

Inventors:

James L. Tucker - Clearwater FL, US
Brian R. Bernier - Tampa FL, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G06F 7/04
G08B 29/00

US Classification:

726 2, 726 34

Abstract:

A system to prevent unauthorized access to a protected device includes a test access port operable to mate with a test access connector, a security key port operable to mate with a security key and a security device in electrical communication with the test access port and the security key port. The protected device is in electrical communication with the test access port when the security device is enabled based on the security key. The test equipment is authorized for access to the protected device when the security device is enabled.

US Patent:

7900064, Mar 1, 2011

Filed:

Nov 4, 2005

Appl. No.:

11/266890

Inventors:

Edwin D. Cruzado - Plant City FL, US
Brian R. Bernier - Tampa FL, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G06F 11/30
G06F 12/14

US Classification:

713194

Abstract:

In one embodiment, a system comprises application-specific functionality, debug functionality, and a debug interface communicatively coupled to the debug functionality to communicatively couple the system to a debug device. The debug functionality encrypts data transmitted by the system over the debug interface.

US Patent:

7961885, Jun 14, 2011

Filed:

Nov 4, 2005

Appl. No.:

11/266792

Inventors:

Edwin D. Cruzado - Plant City FL, US
William J. Dalzell - Parrish FL, US
Brian R. Bernier - Tampa FL, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

H04L 9/00
G06F 9/44

US Classification:

380277, 380280, 714 30, 717124

Abstract:

In one embodiment, a system comprises JTAG functionality that implements at least a portion of a JTAG protocol. The JTAG functionality supports a test data in (TDI) line, a test data out (TDO) line, a test rest (TR) line, a test mode state (TMS) line, and a test clock (TCLK) line. The system further comprises a debug interface to communicatively couple the system to a debug device external to the system. The debug interface comprises a transmit (TX) line, receive (RX) line, and a clock (CLK) line. The system transmits data output by the JTAG functionality on the TDI input on the RX line of the debug interface and receives data from the debug device on the TX line of the debug interface and provides the received data to the JTAG functionality on the TDO line, TR line and the TMS line.

US Patent:

7368935, May 6, 2008

Filed:

Oct 18, 2005

Appl. No.:

11/253006

Inventors:

Brian R. Bernier - Tampa FL, US
Jason Waltuch - St. Petersburg FL, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

H03K 19/00

US Classification:

326 8, 326 9, 326 38

Abstract:

A tamper response system to protect intellectual property is provided. In one embodiment, the tamper response system includes at least one sensor adapted to sense tamper activity and a tamper circuit. The tamper circuit is coupled to receive tamper signals from the at least one sensor. Moreover, the tamper circuit is adapted to clear at least one field programmable gate array (FPGA) upon receipt of a tamper signal.

US Patent:

8011005, Aug 30, 2011

Filed:

Nov 4, 2005

Appl. No.:

11/266877

Inventors:

Edwin D. Cruzado - Plant City FL, US
William J. Dalzell - Parrish FL, US
Brian R. Bernier - Tampa FL, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G06F 7/04
G06F 12/00
G06F 12/14
G06F 13/00
G06F 17/30
G11C 7/00

US Classification:

726 16

Abstract:

In one embodiment, a system comprises application-specific functionality, anti-tamper functionality to detect an unauthorized attempt to interact with the application-specific functionality; and a hardware key interface to communicatively couple the system to a hardware key. An attempt to interact with the application-specific functionality is considered unauthorized if an authorized hardware key is not communicatively coupled to the hardware key interface when the attempt occurs.