Brij Bhushan Garg

US Patent:

6516436, Feb 4, 2003

Filed:

Jan 13, 2000

Appl. No.:

09/483056

Inventors:

Bharat P. Dave - Howell NJ
Adriaan J. De Lind Van Wijngaarden - Basking Ridge NJ
Brij B. Garg - Salem NH
James S. Lavranchuk - Belle Mead NJ
Boris B. Stefanov - Murray Hill NJ
Rudiger L. Urbanke - Murray Hill NJ

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

H03M 1300

US Classification:

714753, 714 18

Abstract:

Error control coding is applied to data streams transmitted through transmission equipment such as a telecommunications switch having a distributed synchronous switch fabric. Each k-symbol dataword is encoded to generate an n-symbol codeword that is then sliced for transmission through the transmission equipment. After routing, error-correction decoding is applied to the resulting routed n-symbol codeword to detect and correct one or more errors in the codeword to generate a k-symbol routed dataword that is identical to the original incoming dataword. Depending on the coding scheme, different types and numbers of errors can be corrected in each codeword. For example, for Reed-Solomon [12, 8, 5] coding with Galois field (2 ), corrections can be made for up to four erasures with no random errors, up to two erasures and one; random error, or up to two random errors with no erasures. In this way, error-less fault tolerance can be provided that ensures the accuracy of transmission processing in the event of certain combinations of errors. Preferred embodiments involve temporal sharing of components (for more cost effective implementations) and shuffling of data (to increase error-correction coverage).

US Patent:

6584121, Jun 24, 2003

Filed:

Nov 13, 1998

Appl. No.:

09/191640

Inventors:

Brij Bhushan Garg - Salem NH
Donald James Wemple - Plymouth VT

Assignee:

Lucent Technologies - Murray Hill NJ

International Classification:

H04J 324

US Classification:

370474, 370369

Abstract:

In a switch in accordance with the principles of the present invention, switch modules that include a disassembly block, a switching core, and an assembly block are combined to implement an NÃM multi-port switch that effectively connects N input ports to M output ports, provides broadcast capability, and may be non-blocking. The switch operates on data channels that all have their respective data blocks organized in the same number of bit-packs. Disassemblers within each module slice incoming data blocks into bit-packs and route the bit-packs to switching cores. A switching core within each module connects each input channel with each output channel at the bit-pack level. Assemblers within each module receive the switched bit-packs from each switching core and assemble the bit-packs into data blocks for each of the output channels.

US Patent:

6970455, Nov 29, 2005

Filed:

Nov 13, 1998

Appl. No.:

09/191708

Inventors:

Brij Bhushan Garg - Salem NH, US
Donald James Wemple - Plymouth VT, US

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

H04L012/50

US Classification:

370357, 370386, 370390, 370432

Abstract:

A switching core in accordance with the principles of the present invention connects N input ports to M output ports and provides multi-cast capability. The switching core includes a plurality of selection blocks, each of which receives multiple input bit packs organized in a combination of input data rails and time slots. The switching core selects one of the input bit packs from one of the rails in one of the time slots and conveys the selected bit pack to an output data position within a combination of output data rails and time slots. This operation may take place both in parallel and in sequence.