Camil B Fayad

US Patent:

6804696, Oct 12, 2004

Filed:

Dec 19, 2000

Appl. No.:

09/740485

Inventors:

Chin-Long Chen - Fishkill NY
Vincenzo Condorelli - Poughkeepsie NY
Camil Fayad - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 738

US Classification:

708491

Abstract:

The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design which includes a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations. A checksum mechanism is also provided to insure accurate operation without impacting speed and without significantly increasing complexity.

US Patent:

6914983, Jul 5, 2005

Filed:

Dec 19, 2000

Appl. No.:

09/740376

Inventors:

Chin-Long Chen - Fishkill NY, US
Vincenzo Condorelli - Poughkeepsie NY, US
Camil Fayad - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F011/00

US Classification:

380 28, 708530

Abstract:

The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations. A checksum mechanism is also provided to insure accurate operation without impacting speed and without significantly increasing complexity.

US Patent:

6978016, Dec 20, 2005

Filed:

Dec 19, 2000

Appl. No.:

09/740245

Inventors:

Chin-Long Chen - Fishkill NY, US
Vincenzo Condorelli - Poughkeepsie NY, US
Camil Fayad - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F007/52
H04L009/30

US Classification:

380 28, 708135, 708209, 708103, 380 30

Abstract:

The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design which includes a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations. A checksum mechanism is also provided to insure accurate operation without impacting speed and without significantly increasing complexity.

US Patent:

7080110, Jul 18, 2006

Filed:

May 7, 2004

Appl. No.:

10/841770

Inventors:

Chin-Long Chen - Fishkill NY, US
Vincenzo Condorelli - Poughkeepsie NY, US
Camil Fayad - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 7/38

US Classification:

708491

Abstract:

The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations. A checksum mechanism is also provided to insure accurate operation without impacting speed and without significantly increasing complexity.

US Patent:

7151829, Dec 19, 2006

Filed:

Apr 22, 2002

Appl. No.:

10/127393

Inventors:

Vincenzo Condorelli - Poughkeepsie NY, US
Camil Fayad - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04K 1/00

US Classification:

380 28, 380 29, 380 30, 380 37, 713180, 713181

Abstract:

A system and method for generating a message digest comprising: receiving a block of data and processing the block of data to achieve a message digest, the processing of the block of data including evaluating the block of data at time (t) in terms of time (t−x), wherein x is greater than or equal to 2.

US Patent:

7783864, Aug 24, 2010

Filed:

Feb 12, 2007

Appl. No.:

11/673752

Inventors:

Camil Fayad - Poughkeepsie NY, US
John K. Li - Woodstock NY, US
Siegfried Sutter - Elsendorf, DE
Tamas Visegrady - Zurich, CH

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/44
G06F 7/38

US Classification:

712221, 708491

Abstract:

The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design which includes a series of nearly identical processing elements linked together in a chained fashion. As a result of simultaneous operation in two subphases per processing element and the chaining together of processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a pardonable chain with separate parts for processing factors of the modulus.

US Patent:

7818574, Oct 19, 2010

Filed:

Sep 10, 2004

Appl. No.:

10/938808

Inventors:

Camil Fayad - Poughkeepsie NY, US
John K. Li - Woodstock NY, US
Siegfried Sutter - Boeblingen, DE

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 9/32

US Classification:

713175, 713173, 713192, 713194, 713156, 726 27, 726 34

Abstract:

A mechanism is provided in which access to the functionality present on an integrated circuit chip is controllable via an encrypted certificate of authority which includes time information indicating allowable periods of operation or allowable duration of operation. The chip includes at least one cryptographic engine and at least one processor. The chip also contains hard coded cryptographic keys including a chip private key, a chip public key and a third party's public key. The chip is also provided with a battery backed up volatile memory which contains information which is used to verify authority for operation. The certificate of authority is also used to control not only the temporal aspects of operation but is also usable to control access to certain functionality that may be present on the chip, such as access to some or all of the cryptographic features provided in conjunction with the presence of the cryptographic engine, such as key size.

US Patent:

7870395, Jan 11, 2011

Filed:

Oct 20, 2006

Appl. No.:

11/551432

Inventors:

Thomas J. Dewkett - Staatsburg NY, US
Camil Fayad - Poughkeepsie NY, US
John K. Li - Woodstock NY, US
Siegfried K. H. Sutter - Elsendorf, DE
Phil C. Yeh - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/14
G06F 15/167
G06F 15/80
G06F 15/82

US Classification:

713189, 713190, 713192, 713193, 709215, 712 10, 712 13, 712 17, 712 27

Abstract:

In an array of groups of cryptographic processors, the processors in each group operate together but are securely connected through an external shared memory. The processors in each group include cryptographic engines capable of operating in a pipelined fashion. Instructions in the form of request blocks are supplied to the array in a balanced fashion to assure that the processors are occupied processing instructions.