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Chandrashekar S Krishnaswamy

age ~60

from Leander, TX

Also known as:
  • Chandrashekar Y Krishnaswamy
  • Shekar S Krishnaswamy
  • Chandrashe Y Krishnaswamy
  • Chandrasheka Krishnaswamy
  • Chanrashekar Krishnaswamy
  • Chandrashekar Krishnawamy
  • Chandrashek Krishnaswamy
  • Chandrash Krishnaswamy

Chandrashekar Krishnaswamy Phones & Addresses

  • Leander, TX
  • 11010 Crossland Dr, Austin, TX 78726 • 5122572819
  • Cedar Park, TX
  • Beacon, NY
  • Travis, TX
  • Fishkill, NY
  • Amherst, MA
  • 11010 Crossland Dr, Austin, TX 78726 • 5126563033

Work

  • Position:
    Production Occupations

Education

  • Degree:
    Bachelor's degree or higher

Emails

Medicine Doctors

Chandrashekar Krishnaswamy Photo 1

Chandrashekar G. Krishnaswamy

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Specialties:
Neurology
Work:
ARH Daniel Boone Clinic Harlan
37 Ball Park Rd, Harlan, KY 40831
6065734520 (phone), 6065748341 (fax)

Neurology Clinic
200 Medical Ctr Dr FL 3, Hazard, KY 41701
6064877955 (phone), 6064870443 (fax)
Education:
Medical School
Mysore Med Coll, Rajiv Gandhi Univ Hlth Sci, Mysore, Karnataka, India
Graduated: 1992
Languages:
English
Description:
Dr. Krishnaswamy graduated from the Mysore Med Coll, Rajiv Gandhi Univ Hlth Sci, Mysore, Karnataka, India in 1992. He works in Harlan, KY and 1 other location and specializes in Neurology. Dr. Krishnaswamy is affiliated with Harlan Appalachian Regional Healthcare Hospital.

Us Patents

  • Automated Integrated Circuit Device Manufacturing Facility Using Distributed Control

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  • US Patent:
    7289867, Oct 30, 2007
  • Filed:
    Jun 8, 2005
  • Appl. No.:
    11/148092
  • Inventors:
    Richard J. Markle - Austin TX, US
    Chandrashekar Krishnaswamy - Austin TX, US
  • Assignee:
    Advanced Micro Devices, Inc. - Austin TX
  • International Classification:
    G06F 19/00
  • US Classification:
    700121
  • Abstract:
    The system includes a plurality of process modules and an independent module controller for each of the plurality of process modules that is adapted to control the process tools within each of the process modules. Each of the independent module controllers performs at least run-to-run control of the processing tools, yield management analysis, scheduling of materials provided to and sent from the process module, and movement of wafers within the process module. One method of the present invention involves providing a plurality of process modules, each of which has an independent module controller that is adapted to perform at least run-to-run control of the processing tools within the process module, yield management analysis, scheduling of materials, and movement of wafers within the process module. The independent module controller for each of the process modules controls the process tools within its respective process module that are employed in forming a portion of the integrated circuit device.
  • Preventative Maintenance Scheduling Incorporating Facility And Loop Optimization

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  • US Patent:
    7444200, Oct 28, 2008
  • Filed:
    Jun 1, 2007
  • Appl. No.:
    11/756710
  • Inventors:
    Peng Qu - Austin TX, US
    Chandrashekar Krishnaswamy - Austin TX, US
  • Assignee:
    Advanced Micro Devices, Inc. - Austin TX
  • International Classification:
    G06F 19/00
  • US Classification:
    700121
  • Abstract:
    A method for scheduling preventative maintenance tasks includes defining a set of global time periods. Members of a set of preventative maintenance tasks associated with a plurality of machines for are scheduled execution during the global time periods based on capacities of the machines and production targets for the machines. A plurality of time slots is defined for a selected global period having a selected preventative maintenance task scheduled for execution therein. A selected time slot from the plurality of time slots is scheduled for performing the selected preventative maintenance task based on work in process levels for with the associated machine over the time slots.
  • Determining Scheduling Priority Using Fabrication Simulation

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  • US Patent:
    7460920, Dec 2, 2008
  • Filed:
    Feb 22, 2006
  • Appl. No.:
    11/359110
  • Inventors:
    Peng Qu - Austin TX, US
    Michael A. Hillis - Austin TX, US
    Dax Middlebrooks - Kyle TX, US
    Farzad Sadjadi - Austin TX, US
    Chandrashekar Krishnaswamy - Austin TX, US
  • Assignee:
    Advanced Micro Devices, Inc. - Austin TX
  • International Classification:
    G06F 19/00
  • US Classification:
    700101, 700100
  • Abstract:
    A method for processing workpieces in a process flow including a plurality of operations includes employing a fabrication simulation model of the process flow to determine an estimated completion time for a selected workpiece. The fabrication simulation model simulates the processing of the selected workpiece and other workpieces in the process flow through the plurality of operations. The priority of the selected workpiece is adjusted based on a comparison between a target completion time for the selected workpiece and the estimated completion time.
  • Determining Scheduling Priority Using Queue Time Optimization

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  • US Patent:
    7623936, Nov 24, 2009
  • Filed:
    Feb 16, 2006
  • Appl. No.:
    11/356267
  • Inventors:
    Peng Qu - Austin TX, US
    Vijay Devarajan - Arlington TX, US
    Michael A. Hillis - Austin TX, US
    Dax Middlebrooks - Kyle TX, US
    Farzad Sadjadi - Austin TX, US
    Chandrashekar Krishnaswamy - Austin TX, US
  • Assignee:
    Advanced Micro Devices, Inc. - Austin TX
  • International Classification:
    G06F 19/00
  • US Classification:
    700101, 700121
  • Abstract:
    A method for determining priority of a selected workpiece in a process flow including a plurality of operations includes providing an objective function relating manufacturing losses to workpiece priority for the operations in the process flow. The objective function is solved to generate priority metrics for at least a subset of the operations remaining for the selected workpiece to allow completion of the selected workpiece in the process flow by a target completion due time.
  • Automated Scheduling Of Test Wafer Builds In A Semiconductor Manufacturing Process Flow

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  • US Patent:
    20090157216, Jun 18, 2009
  • Filed:
    Dec 14, 2007
  • Appl. No.:
    11/956941
  • Inventors:
    CHANDRASHEKAR KRISHNASWAMY - Austin TX, US
    Steven C. Nettles - Johnson City TX, US
    Larry D. Barto - Austin TX, US
  • International Classification:
    G06F 19/00
  • US Classification:
    700121
  • Abstract:
    An automated, computer-implemented method for managing test wafers in an integrated, automated semiconductor manufacturing environment includes: managing a test wafer inventory; consuming inventoried test wafers in the automated process flow; and distributing the consumed test wafers according to their level of usage after an evaluation thereof. An automated, computer-implemented method for use in semiconductor manufacturing includes: monitoring test wafer utilization in an automated process flow; maintaining an inventory of test wafers of a plurality of different types responsive to the monitored utilization; and managing the test wafer utilization of the test wafer inventory. An automated, computer-implemented method for use in semiconductor manufacturing includes: kitting a lot of test wafers; instantiating a software-implemented test lot scheduling agent for the kitted lot, the agent being capable of: scheduling a build for the kitted lot; or scheduling the kitted lot as a resource for consumption in an automated process flow.
  • Determining Metrology Sampling Decisions Based On Fabrication Simulation

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  • US Patent:
    7257502, Aug 14, 2007
  • Filed:
    Feb 28, 2006
  • Appl. No.:
    11/363748
  • Inventors:
    Peng Qu - Austin TX, US
    Chandrashekar Krishnaswamy - Austin TX, US
  • Assignee:
    Advanced Micro Devices, Inc. - Austin TX
  • International Classification:
    H01L 21/00
  • US Classification:
    702 83, 702 82, 702 84, 438 7, 438 8
  • Abstract:
    A method for determining metrology sampling rates for workpieces in a process flow includes determining a current status of the process flow. Future processing of the workpieces in the process flow is simulated based on the current status of the process flow over a predetermined time horizon to predict sampling rates for the workpieces. During the simulating, sampling rules are implemented that consider capacity constraints of a metrology resource in the process flow. Actual workpieces in the process flow are sampled based on the predicted metrology sampling rates.

Youtube

OMKARA.MPG

COMPOSITION OF KALYANI KRISHNASWAMY IN RAAG HINDOLAM (MALKAUNS) TISRA ...

  • Category:
    Music
  • Uploaded:
    20 Feb, 2010
  • Duration:
    6m 6s

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