Charles E Ewers

US Patent:

53315154, Jul 19, 1994

Filed:

Mar 5, 1993

Appl. No.:

8/027053

Inventors:

Charles R. Ewers - Phoenix AZ

Assignee:

SGS-Thomson Microelectronics, Inc. - Carrollton TX

International Classification:

H05K 702

US Classification:

361760

Abstract:

A plurality of integrated circuit devices are bonded to a substrate. Signal traces for corresponding pins of the devices are run to the same location, but are not electrically connected. They are, however, located in close physical proximity at a designated location. At this designated location, a properly shaped and sized contact can be used to contact all of the corresponding traces simultaneously, allowing parallel burn-in of all devices on the substrate to be performed. The devices can still be tested individually after burn-in. Once functionality of the overall subsystem has been confirmed and encapsulation completed, a permanent contact can be made at the designated location to all traces simultaneously so that the devices will be in parallel, and the substrate can be encapsulated to form a completed subsystem.

US Patent:

52397475, Aug 31, 1993

Filed:

Sep 18, 1991

Appl. No.:

7/761372

Inventors:

Charles R. Ewers - Phoenix AZ

Assignee:

SGS-Thomson Microelectronics, Inc. - Carrollton TX

International Classification:

H05K 334

US Classification:

29840

Abstract:

A plurality of integrated circuit devices are bonded to a substrate. Signal traces for corresponding pins of the devices are run to the same location, but are not electrically connected. They are, however, located in close physical proximity at a designated location. At this designated location, a properly shaped and sized contact can be used to contact all of the corresponding traces simultaneously, allowing parallel burn-in of all devices on the substrate to be performed. The devices can still be tested individually after burn-in. Once functionality of the overall subsystem has been confirmed and encapsulation completed, a permanent contact can be made at the designated location to all traces simultaneously so that the devices will be in parallel, and the substrate can be encapsulated to form a completed subsystem.

US Patent:

53152417, May 24, 1994

Filed:

Sep 18, 1991

Appl. No.:

7/761728

Inventors:

Charles R. Ewers - Phoenix AZ

Assignee:

SGS-Thomson Microelectronics, Inc. - Carrollton TX

International Classification:

G01R 3128

US Classification:

324158R

Abstract:

A substrate is provided as a test fixture for burning-in and testing integrated circuit devices. The substrate contains a plurality of unpackaged integrated circuit dice arranged in a regular matrix of rows and columns. The substrate is partitioned into an array of rectangles which can be easily broken apart. One integrated circuit die is attached in each rectangle. The integrated circuits are bonded to conductive traces in their respective rectangular areas, and the conductive traces are connected to common locations at one side of the substrate. Voltages can be applied to all of the devices simultaneously by contacting the common locations at the edge of the substrate. This allows for burn-in of all integrated circuit devices on the substrate in parallel, after which they can be separated and used individually on printed circuit boards.

US Patent:

54615445, Oct 24, 1995

Filed:

Jun 1, 1994

Appl. No.:

8/252456

Inventors:

Charles R. Ewers - Phoenix AZ

Assignee:

SGS-Thomson Microelectronics, Inc. - Carrollton TX

International Classification:

H05K 702

US Classification:

361760

Abstract:

A plurality of integrated circuit devices are bonded to a substrate. Signal traces for corresponding pins of the devices are run to the same location, but are not electrically connected. They are, however, located in close physical proximity at a designated location. At this designated location, a properly shaped and sized contact can be used to contact all of the corresponding traces simultaneously, allowing parallel burn-in of all devices on the substrate to be performed. The devices can still be tested individually after burn-in. Once functionality of the overall subsystem has been confirmed and encapsulation completed, a permanent contact can be made at the designated location to all traces simultaneously so that the devices will be in parallel, and the substrate can be encapsulated to form a completed subsystem.

US Patent:

51754916, Dec 29, 1992

Filed:

Sep 18, 1991

Appl. No.:

7/761693

Inventors:

Charles R. Ewers - Phoenix AZ

Assignee:

SGS-Thomson Microelectronics, Inc. - Carrollton TX

International Classification:

G01R 3100

US Classification:

324158F

Abstract:

A test fixture is provided for simultaneously performing burn-in and testing of multiple integrated circuit devices. The packaged integrated circuits rest on electrical contacts without sockets. A top plate of the fixture holds all of the devices in place. The use of a compressible material allows for variations in package size, lead length, and socket wear while still maintaining good electrical connection. Leads are connected through the test substrate to the backside and the devices may be connected in parallel or otherwise as desired.