Chen Shyh Tsay from 16 Bolton Ct, Danville, CA 94506, age 74

Us Patents

Dual Direction Over-Voltage And Over-Current Ic Protection Device And Its Cell Structure
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US Patent:

6365924, Apr 2, 2002
Filed:

Jun 19, 1998
Appl. No.:

09/100384
Inventors:

Albert Z. H. Wang - Santa Clara CA
Chen H. Tsay - San Jose CA
Peter Deane - Los Altos CA
Assignee:

National Semiconductor Corporation - Santa Clara CA
International Classification:

H01L 2974
US Classification:

257110, 257355, 257362
Abstract:

A two terminal ESD protection structure formed by an alternating arrangement of adjacent p-n-p-n-p semiconductor regions provides protection against both positive and negative ESD pulses. When an ESD pulse appears across the two terminals of the ESD protection structure, one of the inherent n-p-n-p thyristors is triggered into a snap-back mode thereby to form a low impedance path to discharge the ESD current. Some embodiments of the ESD protection structure of the present invention have an enhanced current handling capability and are formed by combining a number of standard cells. The standard cells include a corner cell, a center cell and an edge cell which are arranged adjacent each other to form an ESD protection structure which provides for current flow from across many locations therein. Some embodiments of the ESD protection structure of the present invention include a network consisting of a pair of current sources, e. g. back-to-back zener diodes, each connected in series with a resistor to control the trigger voltage of the ESD protection structure.

Operation Of Dual-Directional Electrostatic Discharge Protection Device
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US Patent:

7327541, Feb 5, 2008
Filed:

Jun 22, 2004
Appl. No.:

10/873031
Inventors:

Albert Z. H. Wang - Santa Clara CA, US
Chen H. Tsay - San Jose CA, US
Peter Deane - Los Altos CA, US
Assignee:

National Semiconductor Corporation - Santa Clara CA
International Classification:

H02H 9/00
H02H 3/00
H01L 29/74
H01L 23/62
H01L 21/332
US Classification:

361 56, 361 51, 257110, 257355, 438133
Abstract:

A two-terminal ESD protection structure formed by an arrangement of five adjacent semiconductor regions (, and ) of alternating conductivity type provides protection against both positive and negative ESD voltages. The middle semiconductor region electrically floats. When the two terminals (A and K) of the ESD protection structure are subjected to an ESD voltage, the structure goes into operation by triggering one of its two inherent thyristors ( and ) into a snap-back mode that provides a low impedance path through the structure for discharging the ESD current.

Dual-Directional Electrostatic Discharge Protection Device
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US Patent:

7936020, May 3, 2011
Filed:

Aug 2, 2007
Appl. No.:

11/890167
Inventors:

Albert Z. H. Wang - Santa Clara CA, US
Chen H. Tsay - San Jose CA, US
Peter Deane - Los Altos CA, US
Assignee:

National Semiconductor Corporation - Santa Clara CA
International Classification:

H01L 23/62
H01L 29/74
H01L 31/111
US Classification:

257355, 257110, 257112, 257122, 257E29005, 257E29014
Abstract:

A two-terminal ESD protection structure formed by an arrangement of five adjacent semiconductor regions (, and ) of alternating conductivity type provides protection against both positive and negative ESD voltages. The middle semiconductor region electrically floats. When the two terminals (A and K) of the ESD protection structure are subjected to an ESD voltage, the structure goes into operation by triggering one of its two inherent thyristors ( and ) into a snap-back mode that provides a low impedance path through the structure for discharging the ESD current.

Dual-Directional Electrostatic Discharge Protection Method
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US Patent:

8305722, Nov 6, 2012
Filed:

Mar 28, 2011
Appl. No.:

13/073990
Inventors:

Albert Z. H. Wang - Santa Clara CA, US
Chen H. Tsay - San Jose CA, US
Peter Deane - Los Altos CA, US
Assignee:

National Semiconductor Corporation - Santa Clara CA
International Classification:

H02H 9/00
H02H 3/00
H01L 29/74
H01L 23/62
H01L 21/332
US Classification:

361 56, 361 51, 257355, 438129, 438133
Abstract:

A two terminal ESD protection structure formed by an alternating arrangement of adjacent p-n-p-n-p semiconductor regions provides protection against both positive and negative ESD pulses. When an ESD pulse appears across the two terminals of the ESD protection structure, one of the inherent n-p-n-p thyristors is triggered into a snap-back mode thereby to form a low impedance path to discharge the ESD current. Some embodiments of the ESD protection structure of the present invention have an enhanced current handling capability and are formed by combining a number of standard cells. The standard cells include a corner cell, a center cell and an edge cell which are arranged adjacent each other to form an ESD protection structure which provides for current flow from across many locations therein. Some embodiments of the ESD protection structure of the present invention include a network consisting of a pair of current sources, e. g. back-to-back zener diodes, each connected in series with a resistor to control the trigger voltage of the ESD protection structure.

Dual Direction Over-Voltage And Over-Current Ic Protection Device And Its Cell Structure
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US Patent:

20020074604, Jun 20, 2002
Filed:

Oct 23, 2001
Appl. No.:

10/045137
Inventors:

Albert Wang - Santa Clara CA, US
Chen Tsay - San Jose CA, US
Peter Deane - Los Altos CA, US
International Classification:

H01L023/62
US Classification:

257/355000
Abstract:

A two terminal ESD protection structure formed by an alternating arrangement of adjacent p-n-p-n-p semiconductor regions provides protection against both positive and negative ESD pulses. When an ESD pulse appears across the two terminals of the ESD protection structure, one of the inherent n-p-n-p thyristors is triggered into a snap-back mode thereby to form a low impedance path to discharge the ESD current. Some embodiments of the ESD protection structure of the present invention have an enhanced current handling capability and are formed by combining a number of standard cells. The standard cells include a corner cell, a center cell and an edge cell which are arranged adjacent each other to form an ESD protection structure which provides for current flow from across many locations therein. Some embodiments of the ESD protection structure of the present invention include a network consisting of a pair of current sources, e.g. back-to-back zener diodes, each connected in series with a resistor to control the trigger voltage of the ESD protection structure.

Method For Manufacturing A Dual-Direction Over-Voltage And Over-Current Ic Protection Device And Its Cell Structure
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US Patent:

62586343, Jul 10, 2001
Filed:

Feb 4, 1999
Appl. No.:

9/246035
Inventors:

Albert Z. H. Wang - Santa Clara CA
Chen H. Tsay - San Jose CA
Peter Deane - Los Altos CA
Assignee:

National Semiconductor Corporation - Santa Clara CA
International Classification:

H01L 21332
US Classification:

438133
Abstract:

A two terminal ESD protection structure formed by an alternating arrangement of adjacent p-n-p-n-p semiconductor regions provides protection against both positive and negative ESD pulses. When an ESD pulse appears across the two terminals of the ESD protection structure, one of the inherent n-p-n-p thyristors is triggered into a snap-back mode thereby to form a low impedance path to discharge the ESD current. Some embodiments of the ESD protection structure of the present invention have an enhanced current handling capability and are formed by combining a number of standard cells. The standard cells include a corner cell, a center cell and an edge cell which are arranged adjacent each other to form an ESD protection structure which provides for current flow from across many locations therein. Some embodiments of the ESD protection structure of the present invention include a network consisting of a pair of current sources, e. g. back-to-back zener diodes, each connected in series with a resistor to control the trigger voltage of the ESD protection structure.