Chi-Yuan Lo

US Patent:

56131020, Mar 18, 1997

Filed:

Oct 19, 1995

Appl. No.:

8/545109

Inventors:

Kuang-Wei Chiang - Easton PA
Chi-Yuan Lo - Basking Ridge NJ
Doowan Paik - Scotch Plains NJ
Shun-Lin Su - Macungie PA

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

G06F 1750

US Classification:

395500

Abstract:

A method of compressing data used in integrated circuit (IC) layout verifications includes the steps of identifying each circuit component from each layer of the IC chip; sorting each circuit component in an established order; identifying predetermined parameters for each component; determining the difference in value of the parameters for each pair of components in successive order; and storing the difference values for each pair of components.

US Patent:

52292312, Jul 20, 1993

Filed:

Aug 30, 1991

Appl. No.:

7/752292

Inventors:

Debaprosad Dutt - Whitehall PA
Chi-Yuan Lo - Basking Ridge NJ

Assignee:

AT&T Bell Laboratories - Murray Hill NJ

International Classification:

G03C 500

US Classification:

430 5

Abstract:

A method is described which reduces the size of the constraint graph used in assembling cells into a tiled module for integrated circuit manufacture. The smaller size significantly reduces the amount of time required to assemble the cells appropriately.