Chris P Lane

US Patent:

6605962, Aug 12, 2003

Filed:

Jan 25, 2002

Appl. No.:

10/057442

Inventors:

Andy L. Lee - San Jose CA
Cameron McClintock - Mountain View CA
Brian Johnson - Sunnyvale CA
Richard Cliff - Los Altos CA
Srinivas Reddy - Fremont CA
Chris Lane - San Jose CA
Paul Leventis - Toronto, CA
Vaughn Timothy Betz - Toronto, CA
David Lewis - Toronto, CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 41, 326 38, 326 39, 716 1, 716 16, 716 17

Abstract:

In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

US Patent:

7000161, Feb 14, 2006

Filed:

Oct 11, 2002

Appl. No.:

10/270800

Inventors:

Tim Allen - Santa Cruz CA, US
Michael Fairman - Santa Cruz CA, US
Mario Guzman - San Jose CA, US
Bryan Hoyer - Boulder Creek CA, US
Chris Lane - San Jose CA, US
Kerry Veenstra - San Jose CA, US
Keith Duwel - San Jose CA, US
Andy L. Lee - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G01R 31/28

US Classification:

714725

Abstract:

A programmable logic system includes a reconfigurable programmable logic device and configuration storage that stores at least two configurations. A default configuration loads first and then loads the desired user application configuration. If the user application configuration fails, the system saves data regarding the failure and then returns to the default configuration for recovery. The default configuration, after reading the failure data, causes an operator to be called to intervene, or loads a different (e. g. , previous) configuration if one is available in configuration storage. The system is particularly useful where the user can update configurations remotely. In an alternative mode, the system stores only the user configuration (which is loaded first) and the default configuration. If a newly-loaded configuration fails, the default configuration is loaded and signals the operator or takes other action short of loading a different configuration.

US Patent:

7058920, Jun 6, 2006

Filed:

Jun 11, 2003

Appl. No.:

10/460685

Inventors:

Andy L. Lee - San Jose CA, US
Cameron McClintock - Mountain View CA, US
Brian Johnson - Sunnyvale CA, US
Richard Cliff - Los Altos CA, US
Srinivas Reddy - Fremont CA, US
Chris Lane - San Jose CA, US
Paul Leventis - Toronto, CA
Vaughn Timothy Betz - Toronto, CA
David Lewis - Toronto, CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 16, 716 10, 716 12, 716 17, 326 39, 326 40, 326 41

Abstract:

In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

US Patent:

7112992, Sep 26, 2006

Filed:

Dec 8, 2004

Appl. No.:

11/008080

Inventors:

Mario Guzman - San Jose CA, US
Chris Lane - San Jose CA, US
Andy L. Lee - San Jose CA, US
Ninh Ngo - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19/173

US Classification:

326 38, 326 39, 326 41

Abstract:

An electronic device comprises a first plurality of configuration elements connected as a shift register for programming a subset of the programmable functions of the electronic device. The subset of programmable functions may be reprogrammed by loading configuration data into the first plurality of configuration elements such that the subset of programmable functions may be reprogrammed without necessarily reprogramming other programmable functions of the electronic device.

US Patent:

7180324, Feb 20, 2007

Filed:

May 28, 2004

Appl. No.:

10/856434

Inventors:

Michael Chan - Scarborough, CA
Paul Leventis - Toronto, CA
David Lewis - Toronto, CA
Ketan Zaveri - San Jose CA, US
Hyun Mo Yi - Mountain View CA, US
Chris Lane - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19/003

US Classification:

326 10, 326 9, 326 41

Abstract:

An embodiment of the present invention provides a programmable logic device (“PLD”) including a redundancy architecture adapted to selective route signals via first or second staggered vertical lines. Other embodiments provide configuration logic and programs for determining routing selections. Other embodiments provide proximate grouping of vertical lines driven from a same row. Other embodiments provide definition of spare row locations once defective row locations are known.

US Patent:

7253660, Aug 7, 2007

Filed:

Nov 27, 2002

Appl. No.:

10/305886

Inventors:

Paul Leventis - Toronto, CA
Bruce Pedersen - San Jose CA, US
Chris Lane - San Jose CA, US
Srinivas Reddy - Fremont CA, US
David Lewis - Toronto, CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L 25/00
H03K 19/177

US Classification:

326 41, 326 37, 326 47, 326113

Abstract:

A multiplexing device is described. In one embodiment, the multiplexing device includes: a hardwired multiplexer including a plurality of input terminals; a plurality of select terminals; and at least one output terminal, where the plurality of input terminals are coupled to a plurality of block input lines or a plurality of functional element input terminals. In one embodiment, the plurality of input terminals are hardwired to the plurality of block input lines or the plurality of functional element input terminals. In one embodiment, the plurality of select terminals are coupled to a second plurality of functional element input terminals or a plurality of functional element output terminals. In one embodiment, the plurality of block input lines include a plurality of logic array block (LAB) lines, the plurality of functional element input terminals include a plurality of logic element (LE) input terminals, and the plurality of functional element output terminals include LE output terminals. In another embodiment the multiplexing device includes: a hardwired multiplexer including a plurality of data signal input terminals; and a first plurality of LEs including a first plurality of LE output terminals, where the plurality of data signal input terminals are coupled to the first plurality of LE output terminals.

US Patent:

7512849, Mar 31, 2009

Filed:

Dec 5, 2005

Appl. No.:

11/294715

Inventors:

Tim Allen - Santa Cruz CA, US
Michael Fairman - Santa Cruz CA, US
Mario Guzman - San Jose CA, US
Bryan Hoyer - Boulder Creek CA, US
Chris Lane - San Jose CA, US
Kerry Veenstra - San Jose CA, US
Keith Duwel - San Jose CA, US
Andy L. Lee - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G01R 31/28
G06F 7/38

US Classification:

714725, 326 38, 326 39

Abstract:

A programmable logic system includes a reconfigurable programmable logic device and configuration storage that stores at least two configurations. A default configuration loads first and then loads the desired user application configuration. If the user application configuration fails, the system saves data regarding the failure and then returns to the default configuration for recovery. The default configuration, after reading the failure data, causes an operator to be called to intervene, or loads a different (e. g. , previous) configuration if one is available in configuration storage. The system is particularly useful where the user can update configurations remotely. In an alternative mode, the system stores only the user configuration (which is loaded first) and the default configuration. If a newly-loaded configuration fails, the default configuration is loaded and signals the operator or takes other action short of loading a different configuration.

US Patent:

7584447, Sep 1, 2009

Filed:

Aug 12, 2005

Appl. No.:

11/202616

Inventors:

Andy L. Lee - San Jose CA, US
Cameron McClintock - Mountain View CA, US
Brian Johnson - Sunnyvale CA, US
Richard Cliff - Los Altos CA, US
Srinivas Reddy - Fremont CA, US
Chris Lane - San Jose CA, US
Paul Leventis - Toronto, CA
Vaughn Timothy Betz - Toronto, CA
David Lewis - Toronto, CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 17/50
H03K 19/177

US Classification:

716 16, 716 1, 716 10, 716 12, 716 17, 326 39, 326 40, 326 41

Abstract:

In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

Author:

Chris Lane

ISBN #:

0340847018

Author:

Chris Lane

ISBN #:

0380977044

Author:

Chris Lane

ISBN #:

0881926787