Daniel Edward Klausmeier

US Patent:

6343075, Jan 29, 2002

Filed:

Oct 26, 1999

Appl. No.:

09/427299

Inventors:

Daniel E. Klausmeier - Menlo Park CA
Jeffrey T. Gullicksen - Santa Clara CA

Assignee:

CIENA Corporation - Linthicum MD

International Classification:

H04L 1250

US Classification:

370388, 359135, 340 221

Abstract:

A switch is provided that includes three stages. The first stages has a plurality of switch circuits. The second stage has a plurality of switch circuits equal to N, where N is any integer other than a power of 2 and where the switch circuits can be logically configured into a logical configuration of a power of 2. The third stages includes a plurality of switch circuits.

US Patent:

6430191, Aug 6, 2002

Filed:

Jun 30, 1997

Appl. No.:

08/885400

Inventors:

Daniel E. Klausmeier - Sunnyvale CA
Kevin Wong - San Jose CA
Quang Nguyen - San Jose CA
Cherng-Ren Sue - San Jose CA
David A. Hughes - Mountain View CA
Ross Suydam Heitkamp - Mountain View CA
Rafael Gomez - Cupertino CA

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H04L 1256

US Classification:

370412, 370468

Abstract:

In a digital switch, incoming cells are placed into a queue in a cell memory. The switch maintains various cell queues, including VC queues that correspond to individual connections and QBin queues that correspond to various classes of service. Cells may arrive to a VC queue or a QBin queue but will depart from a QBin queue. Accordingly, cells may be moved from VC queues to QBin queues. Cells are serviced according to the use of QBin Groups. A QBin Group (QBG) includes a number of logical queues (QBins) of cells to be transported in the digital network. After a QBG is selected, one of its logical queues is selected for servicing. The QBG may be selected by examining all of the QBGs to find an eligible QBG which is most overdue for service. A QBin of the selected QBG may then be selected by examining each of the QBins comprising the selected QBG to find the most overdue for service. The QBGs may correspond to virtual interfaces.

US Patent:

6483854, Nov 19, 2002

Filed:

Jan 30, 2001

Appl. No.:

09/774335

Inventors:

Daniel E. Klausmeier - Sunnyvale CA 94087
Kevin Wong - San Jose CA 95130
David A. Hughes - Mountain View CA 96061

International Classification:

H04J 324

US Classification:

370474, 370412

Abstract:

A plurality of cells are received from a digital network and stored in a logical queue. The cells contain data information and logical connection information and the logical queue corresponds to the logical connection identified by the logical connection information. The cells are combined into a frame by extracting the cells from the logical queue and storing the cells to a local memory so that the data information is preserved. Extraction may be accomplished by notifying a local processor that the frames worth of data is ready and then transferring the data information of the cells to a local memory at the direction of the local processor. During the transfer, error detection operations may be performed. Information may be transmitted into the digital network by segmenting a frame of data into a plurality of cells and injecting each of the cells into a logical queue. The logical queue may be constructed with a series of linked list pointers associated with the memory locations.

US Patent:

6487202, Nov 26, 2002

Filed:

Jun 30, 1997

Appl. No.:

08/884999

Inventors:

Daniel E. Klausmeier - Sunnyvale CA
Kevin Wong - San Jose CA

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H04L 1228

US Classification:

370395, 370233

Abstract:

A method of executing a sequence of multiple dependent operations, each operation including a memory read and a memory write involves overlapping memory accesses of the operations by grouping together memory reads and memory writes of multiple operations and preserving a desired sequence of the operations using a circuit external to a memory through which the memory accesses are performed. The operations may be updates to one or more linked lists. In one embodiment, the step of overlapping memory accesses may be performed by grouping together memory accesses according to ATM cell arrivals or departures. In this embodiment, the operations are associated with ATM cell arrivals or departures and may be gets or puts. Each get and put operation may be characterized by a number of atomic memory operations to update one or more linked lists. To perform the operations a circuit a having an address processor, a data processor coupled to the address processor and to the external memory, and a prefetch buffer coupled to the external memory, the address processor and to the data processor is provided.

US Patent:

6535484, Mar 18, 2003

Filed:

Jan 24, 2000

Appl. No.:

09/490548

Inventors:

David A. Hughes - Mountain View CA
Daniel E. Klausmeier - Sunnyvale CA

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H04L 1256

US Classification:

370230, 370235, 370412

Abstract:

A method of managing oversubscription of a common buffer resource shared by a number of traffic flows in a cell switching network in response to the utilization of the common buffer resource. A buffer utilization threshold is established for each of the traffic flows. As new cells arrive, the global usage of the buffer resource is monitored. As the buffer utilization increases, the thresholds for each of the traffic flows are dynamically adjusted based upon the global usage of the buffer. Aggressive buffer allocations are scaled back when necessary, thereby leaving space for traffic flows which are relatively empty. In one embodiment, the thresholds are coded in mantissa and exponent form so that the scaling is accomplished by adjusting the exponent value.

US Patent:

6714537, Mar 30, 2004

Filed:

Oct 19, 1999

Appl. No.:

09/421059

Inventors:

Joel F. Adam - Cupertino CA
Darren Engelkemier - Mountain View CA
Daniel E. Klausmeier - Menlo Park CA

Assignee:

Ciena Corp. - Linthicum MD

International Classification:

H04J 324

US Classification:

370360, 370388, 340 221, 340 226, 340 26, 379271, 398 53, 398 56

Abstract:

A switch is provided that receives user information through a plurality of framer circuits, which group the user information into frames. The frames are fed to a switch fabric including an array of switch elements, each having a switch matrix for routing each frame to a desired output in accordance with configuration data stored in a first table coupled to the switch matrix. If different outputs are desired, i. e. , the switch matrix is to be reconfigured, a switch control circuit supplies additional switch configuration data to the frames through the inputs along with additional user information to be routed through the switch. While the additional switch configuration data is stored in a second table, data flow remains uninterrupted through the switch matrix. Once storage of the additional configuration data into the second table is complete, however, the switch control circuit inserts a table select signal into the frames, to thereby couple the second table to the switch so that the switch matrix is configured in accordance with the additional switch configuration data. Subsequent frames are then routed through the reconfigured switch matrix.

US Patent:

7016357, Mar 21, 2006

Filed:

Oct 26, 1999

Appl. No.:

09/427300

Inventors:

Tom Q. Wellbaum - Beaverton OR, US
Daniel E. Klausmeier - Menlo Park CA, US

Assignee:

CIENA Corporation - Linthicum MD

International Classification:

H04L 12/56

US Classification:

37039551, 370474, 370475, 370907

Abstract:

Switch frames are arbitrarily concatenated to allow for any available time slots to be used for carrying concatenated switch frames. Methods and apparatus transport switch frames in available time slots, and keep track of which time slots correspond to a group of concatenated switch frames. The switch frames are transported through the switch and synchronized on the outgoing side of the switch so that arbitrarily concatenated switch frames are synchronized with each other.

US Patent:

7020135, Mar 28, 2006

Filed:

Dec 17, 2001

Appl. No.:

10/023971

Inventors:

Daniel E. Klausmeier - Menlo Park CA, US
Jeffrey T. Gullicksen - Santa Clara CA, US

Assignee:

CIENA Corporation - Linthicum MD

International Classification:

H04L 12/50

US Classification:

370388, 340 221

Abstract:

A switch is provided that includes three stages. The first stages has a plurality of switch circuits. The second stage has a plurality of switch circuits equal to N, where N is any integer other than a power of 2 and where the switch circuits can be logically configured into a logical configuration of a power of 2. The third stages includes a plurality of switch circuits.