Darrin Benzer - Chandler AZ Robert F. Elio - Mesa AZ
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03L 500
US Classification:
327333, 327427, 326 68, 326 81
Abstract:
Systems and methods are disclosed for a multi-level level shifter circuit having a single ended input and adapted to translate one or more signals from one voltage level to another. More specifically, the present invention provides a level shifter that doesnt require a complementary input or an additional power supply if the complementary signal isnt available. One embodiment of the level shifter circuit device having a single-ended input comprises at least three transistor devices. The first transistor device is coupled to at least the input and is adapted to have a threshold voltage less than 0V. The second transistor device is coupled to at least the first transistor device, while a level shifter transistor device is coupled to at least the first and second transistor devices.
5 Volt Tolerant Io Scheme Using Low-Voltage Devices
Kent Oertle - Phoenix AZ, US Robert Elio - Mesa AZ, US Duncan McFarland - Tempe AZ, US Darrin Benzer - Chandler AZ, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03K019/0175
US Classification:
326 81, 326 82, 326 83, 326 27
Abstract:
Systems and methods are disclosed for operating a core circuitry of an integrated circuit at a lower voltage than the coupled IO circuitry using a tolerant circuit. In one embodiment includes a voltage tolerant circuit comprising a voltage detect module adapted to detect when a voltage is sufficient to switch bias conditions without violating maximum transistor operating conditions and a comparator adapted to detect when a PAD voltage is greater than an IO power supply voltage.
Method And Apparatus For A Fully Differential Amplifier Output Stage
The input stage of the fully differential amplifier output stage is configured in a differential pair configuration with a tail current. The tail current is divided between two legs of the input stage and is higher in the leg that has the higher of the two input voltage levels (in or inb). The devices in each leg of the fully differential amplifier output stage may be cascoded to avoid electrical voltage overstress. The top device in each leg of the differential input stage may be coupled in a diode configuration and is utilized to mirror the current into another NMOS current mirror as well as to a PMOS output device. The gate of the PMOS output devices are connected in a cross-coupled configuration. The NMOS current mirrors are utilized to mirror the current into the NMOS output devices in a non-cross-coupled configuration.
Kent Oertle - Phoenix AZ, US Robert Elio - Mesa AZ, US Duncan McFarland - Tempe AZ, US Darrin Benzer - Chandler AZ, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03K 19/0175
US Classification:
326 81, 326 83, 326 26
Abstract:
Systems and methods are disclosed for reducing or eliminating hot carrier injection stress in circuits. In one embodiment, the present invention relates to an integrated circuit comprising an IO PAD, an output circuit coupled to at least the IO PAD and a stress circuit. The stress circuit is coupled to at least the output circuit and is adapted to limit a high voltage across the output circuit when the output circuit is enabled, thereby reducing stress on the output circuit. In one embodiment, the stress circuit comprises at least one transistor device (a p-channel device or two stacked p-channel devices, for example) and the output circuit comprises a transistor device (an n-channel device or two stacked n-channel devices).
Darrin Benzer - Chandler AZ, US Robert F. Elio - Mesa AZ, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03L 5/00
US Classification:
327333, 326 68, 326 81
Abstract:
Methods are disclosed for translating or shifting a voltage level of a single ended input. More specifically, the present invention provides a method of translating or shifting a voltage level that doesn't require a complementary input or an additional power supply if the complementary signal isn't available. One embodiment of the method of translating a voltage level of a single-ended input signal using at least one native transistor device having a threshold voltage less than 0V comprises outputting a first voltage level if the single ended input signal is in a first state. A second voltage level is output if the single ended input is in a second state.
5 Volt Tolerant Io Scheme Using Low-Voltage Devices
Kent Oertle - Phoenix AZ, US Robert Elio - Mesa AZ, US Duncan McFarland - Tempe AZ, US Darrin Benzer - Chandler AZ, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03K 19/0175
US Classification:
326 83, 326 81
Abstract:
Systems and methods are disclosed for operating a core circuitry of an integrated circuit at a lower voltage than the coupled IO circuitry using a tolerant circuit. In one embodiment includes a voltage tolerant circuit comprising a voltage detect module adapted to detect when a voltage is sufficient to switch bias conditions without violating maximum transistor operating conditions and a comparator adapted to detect when a PAD voltage is greater than an IO power supply voltage.
Low Voltage Input Level Shifter Circuit And Method For Utilizing Same
According to one embodiment, a level shifter circuit operable with a low voltage input comprises first and second pull-down switches configured to receive the low voltage input as respective non-inverted and inverted control voltages, first and second pull-up switches coupled between the respective first and second pull-down switches and an output supply voltage, and a pull-up boost switching stage coupled to a node between the first pull-up switch and the first pull-down switch. The pull-up boost switching stage is configured to turn ON in response to the second pull-down switch turning ON, and to turn OFF before the first pull-up switch turns OFF. In one embodiment, the level shifter circuit may be implemented as part of an input/output (IO) pad of an integrated circuit (IC) fabricated on a semiconductor die.
Systems and methods are disclosed for a clamping circuit for protecting against voltage overstresses. One embodiment of the system comprises a first voltage comparator adapted to detect when a selected voltage exceeds a first predetermined voltage and a second voltage comparator adapted to detect when the selected voltage falls below a second predetermined voltage, thereby preventing voltage overstresses.