David X Dong

Address:

505 Montclair Dr NE, Albany, OR 97322

Phone:

4254278568

VIN:

JTEBU5JR5C5106910

Make:

TOYOTA

Model:

4RUNNER

Year:

2012

Address:

42932 Via Valparaiso, Fremont, CA 94539

Phone:

5106231907

VIN:

4JGBF71E87A160279

Make:

MERCEDES-BENZ

Model:

GL-CLASS

Year:

2007

US Patent:

6362767, Mar 26, 2002

Filed:

Mar 22, 1999

Appl. No.:

09/274202

Inventors:

David Xiao Dong Yang - Palo Alto CA
Boyd Fowler - Sunnyvale CA
Abbas El Gamal - Palo Alto CA

Assignee:

The Board of Trustees of the Leland Stanford Junior University - Stanford CA

International Classification:

H03M 112

US Classification:

341155, 341169, 348571

Abstract:

A method of simultaneously providing A/D conversion and multiplication in a Bit-Serial ADCs and single slope ADCs. A bit serial ADC uses a RAMP signal and a BITX signal input to a comparator and 1-bit latch, respectively. When RAMP exceeds an analog input value, the comparator triggers the latch to output the value of BITX. The bits are output serially. The RAMP signal has a staircase shape with voltage levels and voltage steps. In the present invention, multiplication by two coefficients is possible. One coefficient is determined by properly designing RAMP, and the other coefficient is determined by properly designing BITX. Multiplication via RAMP is accomplished by changing the voltage levels by a factor of 1/X, where X is the multiplying coefficient (i. e. , multiplication by a factor of 0. 5 is accomplished by doubling the voltage of the voltage levels).

US Patent:

6498576, Dec 24, 2002

Filed:

Mar 30, 2001

Appl. No.:

09/823344

Inventors:

Hui Tian - Stanford CA
David Xiao Dong Yang - Mountain View CA

Assignee:

Pixim, Inc. - Mountain View CA

International Classification:

H03M 112

US Classification:

341155, 341156, 341139, 341122, 341 14, 341160, 341161, 348294, 348297

Abstract:

A system and method for performing low-power analog-to-digital conversion in digital imaging system utilizing a time-indexed multiple sampling technique is presented. The analog-to-digital converter is switched off when the digital image signal resulting from an exposure time selected from a plurality of exposure times satisfies a threshold value.

US Patent:

6518909, Feb 11, 2003

Filed:

Sep 25, 2001

Appl. No.:

09/965600

Inventors:

David Xiao Dong Yang - Mountain View CA
William R. Bidermann - Los Gotos CA

Assignee:

Pixim, Inc. - Mountain View CA

International Classification:

H03M 138

US Classification:

341155, 341136, 341169, 341159, 341161, 341150, 341152, 327 65, 327563

Abstract:

A circuit includes an analog-to-digital (A/D) converter for multiplexing between a number of analog input signals and converting the selected analog input signals to a digital code representation. The A/D converter includes a comparator having a first input terminal connected to receive the first signal having a number of levels, a second input terminal connected to receive a multiple number of analog input signals, and a third input terminal for receiving a multiple number of input select signals. The comparator includes a multiplexer coupling the multiple number of analog input signals to a multiple number of corresponding input signal paths. The multiplexer selects one of the multiple number of input signal paths based on the multiple number of input select signals. In one embodiment, the A/D converter is applied in a digital image sensor for performing pixel-level analog-to-digital conversion using a multi-channel bit serial ADC technique.

US Patent:

6693575, Feb 17, 2004

Filed:

May 17, 2002

Appl. No.:

10/150553

Inventors:

David Xiao Dong Yang - Mountain View CA
William R. Bidermann - Los Gatos CA

Assignee:

Pixim, Inc. - Mountain View CA

International Classification:

H03M 112

US Classification:

341155, 341161, 341156, 341136, 341159, 348294, 348297, 348227

Abstract:

A multi-channel bit-serial analog-to-digital converter with reduced channel circuitry is described herein in which a one-bit comparator circuit is split between a first part located within an input channel and a second part located outside the input channel. The external part of the comparator and the one-bit latch are shared by a plurality of input channels. In the preferred embodiment, a two-dimensional sensor array of pixel elements is fabricated in a single integrated circuit. Each of the pixel elements is an input channel which comprises a photodetector and the front-end part of the one-bit comparator. The external part of the comparator and the one-bit latch are formed in the periphery of the sensor array and are shared by a group of pixel elements, such as a column of pixel elements. In one embodiment, by connecting the output of an inverter to the control signal terminal of the comparator, the comparator can also be used as a buffer for analog readout. This creates an analog read port for minimum amount of circuitry increase.

US Patent:

6765619, Jul 20, 2004

Filed:

Apr 4, 2000

Appl. No.:

09/542196

Inventors:

Zhonghan Deng - Albany CA
David Xiao Dong Yang - Mountain View CA
Xi Peng - Milpitas CA
Odutola Oluseye Ewedemi - San Jose CA
Ricardo Jansson Motta - Palo Alto CA
Yi-Hen Wei - San Jose CA

Assignee:

PIXIM, Inc. - Mountain View CA

International Classification:

H04N 5235

US Classification:

348362, 348297

Abstract:

A method of optimizing the exposure times of regions of pixels of an image sensor array during exposure is accomplished by utilizing time interval sampling of an image sensor array comprising of pixels configured to generate digital image signals. Luminance values are extracted from each digital image signal and analyzed to determine if a pixel has reached the optimal exposure. If a pixel has reached the optimal exposure, subsequent digital image signals from this pixel will not be recorded. This preserves the recording of the optimal digital image signal generated by the pixel at the time when the pixel reached its optimal exposure. This process of selectively terminating the recording of digital image signals based on optimal exposures of the pixels can be performed on individual pixels or can be performed on a region of pixels.

US Patent:

6778212, Aug 17, 2004

Filed:

Sep 19, 2000

Appl. No.:

09/665523

Inventors:

Zhonghan John Deng - Mountain View CA
David Xiao Dong Yang - Mountain View CA
Odutola Oluseye Ewedemi - San Jose CA

Assignee:

Pixim, Inc. - Mountain View CA

International Classification:

H04N 5228

US Classification:

3482221, 348294, 348308, 2502081

Abstract:

An image sensor, including a substrate having formed thereon by a CMOS process a digital sensor array having a plurality of digital pixel sensors which output analog signals corresponding to a desired image. The digital sensor array further includes supporting circuitry for converting the analog signals produced by the digital pixel sensors to digital signals corresponding to the desired image. Filter circuitry, for converting the digital signals to digital values representative of the light intensity impinging upon the plurality of digital pixel sensors, is also formed on the substrate using CMOS fabrication processes. Memory devices, including a data memory, a threshold memory, and a time index memory are formed on the substrate using CMOS fabrication techniques. A clock circuit is also formed on the substrate using CMOS fabrication processes. Programmable logic structures are formed on the substrate using CMOS fabrication processes.

US Patent:

6788240, Sep 7, 2004

Filed:

Jul 11, 2003

Appl. No.:

10/618398

Inventors:

Justin Reyneri - Los Altos CA 94024
David Xiao Dong Yang - Mountain View CA 94306

International Classification:

H03M 136

US Classification:

341159, 341155

Abstract:

A circuit includes an input terminal coupled to receive an analog input signal, a multiple number of sample-and-hold circuits and a multiple number of analog-to-digital (A/D) converters. The input terminal of each of the sample-and-hold circuits is coupled to receive the analog input signal. Each of the A/D converters has an input terminal and an output terminal, where the input terminal is coupled to an output terminal of a corresponding one of the sample-and-hold circuits. In operation, the sample-and-hold circuits sample the analog input signal sequentially and store a multiple number of analog samples at each of the sample-and-hold circuits. The A/D converters convert the analog samples in parallel to generate digital values at the output terminals of each of the A/D converters representative of each of the analog samples. In one embodiment, the A/D converters are implemented based on a multi-channel bit-serial (MCBS) analog-to-digital conversion scheme.

US Patent:

6791611, Sep 14, 2004

Filed:

May 23, 2001

Appl. No.:

09/864296

Inventors:

David Xiao Dong Yang - Mountain View CA

Assignee:

Pixim, Inc. - Mountain View CA

International Classification:

H04N 314

US Classification:

348302, 348308, 348294, 3482319

Abstract:

An image sensor architecture that accommodates the relative mismatch of bus width between the image sensor, processor, and memory is disclosed. The preferred embodiment of the invention provides a dual-ported memory structure having a relatively wide data port for receiving data from the image sensor and having a relatively narrow data port for communicating data to and from the processor. In one embodiment of the invention, the memory is organized into banks of a specific width. The banks may be accessed sequentially by the processor, such that the bus width is equivalent to the bank width, and the banks may be accessed simultaneously, such that the bus width is equivalent to the combined bank widths. A simple switching means, operating under processor control, reconfigures the memory on the fly.