David W Hansquine

US Patent:

6366600, Apr 2, 2002

Filed:

Dec 14, 1998

Appl. No.:

09/211989

Inventors:

Avneesh Agrawal - Sunnyvale CA
David Hansquine - San Diego CA
Paul E. Bender - San Diego CA

Assignee:

Qualcomm Incorporated - San Diego CA

International Classification:

H04B 169

US Classification:

375130

Abstract:

A spreader architecture for direct sequence spread spectrum communications is disclosed. This single architecture can perform OOK, BPSK, or QPSK spreading modulation of a carrier. In the QPSK and BPSK modes, input data is spread by pseudonoise signals to produce digital representations of phase-modulated baseband in-phase and quadrature components. In the OOK mode, the spectrum of the baseband components is selectively spread according to the input data. In an exemplary application, the various modulation modes are used to encode the control and traffic channels of a code-division multiple-access cellular telephone system.

US Patent:

6493354, Dec 10, 2002

Filed:

Nov 11, 1998

Appl. No.:

09/189710

Inventors:

David Hansquine - San Diego CA
Avneesh Agrawal - Sunnyvale CA

Assignee:

Qualcomm, Incorporated - San Diego CA

International Classification:

H04J 316

US Classification:

370468, 370537, 709226

Abstract:

A resource allocator for allocating at least two different types of hardware resources for users within a communication system, wherein the system supports up to a first predetermined number of users of one particular type and a second predetermined number of users of a second particular type. The resource allocator provides a mapping of resources, either from fixed resources to shared resources or from shared resources to fixed resources, which is both cost effective and transparent to software.

US Patent:

6519297, Feb 11, 2003

Filed:

Dec 20, 2000

Appl. No.:

09/741969

Inventors:

Brian K. Butler - La Jolla CA
Gwain Bayley - San Diego CA
David Hansquine - San Diego CA

Assignee:

Qualcomm, Incorporated - San Diego CA

International Classification:

H04L 2706

US Classification:

375341, 714786

Abstract:

The certainties of transmitted bits at predetermined locations in time are determined a priori. This information is then used to set the states of a Viterbi decoder to different state metrics in accordance with the certainties of the transmitted bits. High certainty of a transmitted bit results in resetting the states corresponding to that bit to a high state metric. In contrast, low certainty of a transmitted bit results in resetting the states corresponding to that bit to a low state metric. Resetting the states to different state metrics improves the decoding performance and shortens the time required to converge the decoding trellis by eliminating improbable paths.

US Patent:

6757864, Jun 29, 2004

Filed:

Apr 6, 2000

Appl. No.:

09/544324

Inventors:

David W. Hansquine - San Diego CA

Assignee:

QUALCOMM, Incorporated - San Diego CA

International Classification:

H03M 1300

US Classification:

714794, 375341

Abstract:

The present invention discloses a method and apparatus for efficiently reading and storing state metrics in memory to enhance high-speed ACS Viterbi decoder implementations. The method includes applying an addressing scheme that determines the address locations of source state metrics during a process cycle. The source state metrics are then read from the address locations during the process cycle and applied to an add-compare-select butterfly operation of a Viterbi algorithm implementation to generate target state metrics. The method then stores each of the target state metrics into the address locations previously occupied by the source state metrics. The method further provides an addressing scheme that determines the address locations of the source state metrics based on a process cycle counter that is incremented and rotated in accordance with the process cycle. The method also provides an addressing scheme that employs a predetermined function to determine the address locations of the source state metrics.

US Patent:

7184915, Feb 27, 2007

Filed:

Jul 29, 2003

Appl. No.:

10/630516

Inventors:

David W. Hansquine - San Diego CA, US
Roberto F. Averbuj - San Diego CA, US

Assignee:

Qualcomm, Incorporated - San Diego CA

International Classification:

G01R 31/00

US Classification:

702118, 714718

Abstract:

A distributed, hierarchical built-in self-test (BIST) architecture for testing the operation of one or more memory modules is described. As described, the architecture includes three tiers of abstraction: a centralized BIST controller, a set of sequencers, and a set of memory interfaces coupled to memory modules. The BIST controller stores a set of commands that generically define an algorithm for testing the memory modules without regard to the physical characteristics or timing requirements of the memory modules. The sequencers receive the commands and generate sequences of memory operations in accordance with the timing requirements of the various memory modules. The memory interfaces apply the memory operations to the memory module in accordance with physical characteristics of the memory module, e. g. , by translating address and data signals based on the row-column arrangement of the memory modules to achieve bit patterns described by the commands.

US Patent:

7392442, Jun 24, 2008

Filed:

Jul 29, 2003

Appl. No.:

10/630480

Inventors:

Roberto Fabian Averbuj - San Diego CA, US
David W. Hansquine - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G11C 29/00

US Classification:

714718, 702118

Abstract:

A built-in self-test (BIST) architecture having distributed algorithm interpretation is described. The architecture includes three tiers of abstraction: a centralized BIST controller, a set of sequencers, and a set of memory interfaces. The BIST controller stores a set of commands that generically define an algorithm for testing memory modules without regard to the physical characteristics or timing requirements of the memory modules. The sequencers interpret the commands in accordance with a command protocol and generate sequences of memory operations. The memory interfaces apply the memory operations to the memory module in accordance with physical characteristics of the memory module, e. g. , by translating address and data signals based on the row-column arrangement of the memory modules to achieve bit patterns described by the commands. The command protocol allows powerful algorithms to be described in an extremely concise manner that may be applied to memory modules having diverse characteristics.

US Patent:

7814380, Oct 12, 2010

Filed:

May 18, 2008

Appl. No.:

12/122702

Inventors:

Roberto Fabian Averbuj - San Diego CA, US
David W. Hansquine - Raleigh NC, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G11C 29/00

US Classification:

714718, 702118

Abstract:

Built-in self-test (BIST) architecture having distributed interpretation and generalized command protocol is disclosed. In an embodiment, a system is disclosed and includes a centralized built-in self-test (BIST) controller configured to store an algorithm to test a plurality of memory modules. The BIST controller stores the algorithm as a set of generalized commands that conform to a command protocol. The BIST controller is configured to send the set of generalized commands to a sequencer.

US Patent:

20050259609, Nov 24, 2005

Filed:

May 20, 2004

Appl. No.:

10/851787

Inventors:

David Hansquine - San Diego CA, US
Brett Walker - San Diego CA, US
Muhammad Muneer - San Diego CA, US

International Classification:

H04L012/50

US Classification:

370328000

Abstract:

Embodiments disclosed herein address the need for a single wire bus interface. In one aspect, a device communicates with a second device via a single wire bus using a driver for driving the bus with a write frame comprising a start symbol, a write indicator symbol, an address, and data symbols. In another aspect, the device receives one or more data symbols on the single wire bus during a read frame. In yet another aspect, a device communicates with a second device via a single wire bus using a receiver for receiving a frame on the single wire bus comprising a start symbol, a write indicator symbol, an address, and one or more data symbols, and a driver for driving return read data associated with the address when the write indicator identifies a write frame. Various other aspects are also presented. These aspects provide for communication on a single wire bus, which allows for a reduction in pins, pads, or inter-block connections between devices.