David W Marquart

US Patent:

50797255, Jan 7, 1992

Filed:

Nov 17, 1989

Appl. No.:

7/438746

Inventors:

Charles P. Geer - Rochester MN
David W. Marquart - Rochester MN

Assignee:

IBM Corporation - Rochester MN

International Classification:

G06F 1300

US Classification:

364550

Abstract:

A method and apparatus are provided for uniquely identifying integrated circuit chips adapted for use with scan design systems and scan testing techniques. A predetermined identification number corresponding to each LSI chip to be identified is assigned. Each predetermined identification number has a predefined format. The assigned identification number is stored in a plurality of predefined shift register latches (SRLs) in the corresponding LSI chip to be identified. Then the LSI chip is identified by selectively reading out the stored predetermined identification number.

US Patent:

56491778, Jul 15, 1997

Filed:

Nov 28, 1995

Appl. No.:

8/563561

Inventors:

Lyle Edwin Grosbach - Rochester MN
David John Krolak - Dodge Center MN
David Wayne Marquart - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 110

US Classification:

395560

Abstract:

The ability to harmonize the activities of individual computer system components with control signals is key to the operation of any computer system. Examples of this need for control include the need to write data to multiple registers on the same clock cycle, the need to clear values on multiple entities on the same clock cycle, and the need to stop and start the master clock pulse train itself. In the past, providing this control was not a problem because control signals could be reliably sent to all the timing dependent components within a single cycle of the master clock pulse train. This control methodology is called "single cycle control. " Today, however, single cycle control is not trustworthy in all situations. Master clock pulse trains are so fast that single cycle control is no longer reliable when timing dependent components reside in locations distant from the control signal generating circuitry. The present invention provides reliable control in all cases, including the situation where a master clock pulse train is so fast that single cycle control is not viable.

US Patent:

51466058, Sep 8, 1992

Filed:

Jan 23, 1991

Appl. No.:

7/644799

Inventors:

Bruce L. Beukema - Hayfield MN
David W. Marquart - Rochester MN
Ronald D. Morse - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 900

US Classification:

395575

Abstract:

Control panel function is provided to bus units coupled together by an I/O bus. At least one bus unit has the capability to issue control commands through the bus to one or more other bus units. A control facility is integrated into bus units, and makes full use of existing paths to processor registers and main storage. Control commands are distinguished from other bus communications, and executed by the control facility, to provide a full control panel function for each bus unit incorporating the control facility.

US Patent:

49300695, May 29, 1990

Filed:

Nov 18, 1987

Appl. No.:

7/122294

Inventors:

Surinder P. Batra - Rochester MN
William E. Hammer - Rochester MN
Gene A. Lushinsky - Mantorville MN
David W. Marquart - Rochester MN
Walter H. Schwane - Kasson MN
Frederick J. Ziecina - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1516
G06F 1300

US Classification:

364200

Abstract:

The flow of work requests in a server driven process to process communication environment is described. A mechanism is provided to facilitate work consistent with the server driven architecture when bus units do not have adequate DMA capabilities. Two ways of reversing control of transfer of work requests and data so that the server need not have master DMA capability are presented. Management of storage in a remote processor is used to transfer work and its associated data into storage accessible by a bus unit with slave DMA capability. The slave DMA bus unit then transfers the information into storage is manages. In another way of reversing the flow, a bus unit message is used to make the original server a requestor. The bus unit message contains information which varies the request sent by the requestor. In this manner, the server, which was the original requestor transfers information using its master DMA capability flow.