David Anthony Mcintyre

Author:

David McIntyre

ISBN #:

0533090237

Author:

David J. McIntyre

ISBN #:

0801615526

US Patent:

6678197, Jan 13, 2004

Filed:

Oct 18, 2002

Appl. No.:

10/273623

Inventors:

Frederick A. Perner - Palo Alto CA
Kenneth K. Smith - Boise ID
David H. McIntyre - Boise ID
Sarah M. Brandenberger - Boise ID
Terrel R. Munden - Boise ID
Robert Sesek - Meridian ID

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G11C 702

US Classification:

365206, 365207, 36518901, 365158

Abstract:

Systems and methods for reducing the effect of noise while reading data from memory, are provided. One system embodiment includes a memory cell that stores a first data; multiple sensing devices that receive the first data and provide a first set of outputs; and a voting system that evaluates the first set of outputs to determine whether one of the outputs of the first set is valid data from the memory cell. One method embodiment includes reading data in parallel that is stored in a memory cell to provide outputs; and evaluating the outputs to determine whether one of the outputs is valid data from the memory cell.

US Patent:

6717874, Apr 6, 2004

Filed:

Aug 14, 2002

Appl. No.:

10/218892

Inventors:

Frederick A. Perner - Palo Alto CA
David H. McIntyre - Boise ID
Jonathan Jedwab - London, GB
Anthony P. Holden - Boise ID

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G11C 702

US Classification:

365206, 36518901

Abstract:

Systems and methods for reducing the effect of noise while reading data in series from memory, are provided. One system embodiment comprises a memory cell that stores a first data; a sensing device that receives the first data multiple times and provides a first set of outputs; and a voting system that evaluates the first set of outputs to determine whether one of the outputs of the first set is valid data from the memory cell. One method embodiment comprises reading data in series that is stored in a memory cell to provide outputs; and evaluating the outputs to determine whether one of the outputs is valid data from the memory cell.

US Patent:

6999366, Feb 14, 2006

Filed:

Dec 3, 2003

Appl. No.:

10/727273

Inventors:

Frederick A. Perner - Palo Alto CA, US
Jonathan Jedwab - Vancouver, CA
James A. Davis - Richmond VA, US
David McIntyre - Boise ID, US
David Banks - Bristol, GB
Stewart Wyatt - Boise ID, US
Kenneth K. Smith - Boise ID, US

Assignee:

Hewlett-Packard Development Company, LP. - Houston TX

International Classification:

G11C 7/02

US Classification:

365209, 365158

Abstract:

Embodiments of the present invention provide a magnetic memory. In one embodiment, the magnetic memory comprises an array of memory cells configured to provide resistive states, and a read circuit. The read circuit is configured to sense a resistance through a memory cell in the array of memory cells to obtain a sense result and categorize the sense result into one of at least three different categories comprising a middle category situated between the resistive states.

US Patent:

7215175, May 8, 2007

Filed:

Sep 1, 2004

Appl. No.:

10/932162

Inventors:

Gurupada Mandal - Santa Clara CA, US
Suresh Seshadri - Mountain View CA, US
David Hugh McIntyre - Sunnyvale CA, US
Raymond A. Heald - Los Altos CA, US
William Y. Mo - Los Altos CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H01H 37/76
H01H 85/00

US Classification:

327525

Abstract:

An improved circuit for sensing and programming fuses in integrated circuits. The circuit is broadly comprised of a fuse cell, a reference circuit, a sense amplifier and a level detector. In one embodiment of the present invention, a two-stage sensing scheme is implemented. The improved fuse sensing circuit uses current-mode sensing and implements an auto-read current reduction scheme. Using a level-detect circuit, the virtual ground is raised automatically if the high-voltage power supply exceeds core supply (Vdd) by a fixed dc voltage. This reduces effective sensing voltage and the read current and thus helps preserve unblown fuse integrity. In one embodiment of the invention, four modes of operation are implemented: “Normal Read,” “Unblown_Read,” “Blown_Read_1” and “Blown_Read_2. ” The default read mode is the “normal read” while the “Unblown” and “Blown” read modes are for fuse calibration purposes. In the “Unblown_Read” read mode, the circuit is operable to compare the fuse resistance against a lower reference resistance, closer to an unblown fuse resistance value, in order to make the comparison more stringent.

US Patent:

8374039, Feb 12, 2013

Filed:

Dec 22, 2010

Appl. No.:

12/975718

Inventors:

David Hugh McIntyre - Sunnyvale CA, US
Jimmy L. Reaves - San Jose CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 7/06

US Classification:

36518907, 36523003, 36523005, 36523001

Abstract:

A multi-port memory array is disclosed. The memory array includes a plurality of memory subblocks and an output network. Each memory subblock includes a plurality of single-read-port memory cells. The output network is configured to redirect information read for a first read port to a second read port on a condition that an equivalence signal indicates that read addresses for the first read port and the second read port are the same. The latching and multiplexing operation may be integrated. The memory cells may be 6-transistor synchronous random access memory (SRAM) cells, 8-transistor SRAM cells, or any type of memory cells.

US Patent:

8503210, Aug 6, 2013

Filed:

Dec 22, 2010

Appl. No.:

12/975601

Inventors:

Mandeep Singh - Austin TX, US
David Hugh McIntyre - Sunnyvale CA, US
Hung Phuong Ngo - San Jose CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 15/04
G11C 15/00

US Classification:

365 4917, 365 491, 365203, 711108

Abstract:

A conditionally precharged content addressable memory (CAM) includes forcing a mismatch on a matchline of the CAM if a data entry in the CAM is invalid. The matchline of the CAM is precharged only if the data entry is valid.

US Patent:

20040156554, Aug 12, 2004

Filed:

Oct 15, 2003

Appl. No.:

10/687525

Inventors:

David McIntyre - Issaquah WA, US

International Classification:

G06K009/40

US Classification:

382/254000

Abstract:

A system and method for simulating defects of visual function are provided. In one aspect, the invention provides a computer system for simulating visual defects including a device for obtaining an input image, a memory, a processing unit, means for modifying the input image to simulate a visual defect, and a display device. In another aspect, the invention provides methods for simulating a visual defect to a user which involves obtaining an input image, selecting a visual defect filter set to apply, processing and displaying the modified image.

US Patent:

20120137109, May 31, 2012

Filed:

Nov 30, 2010

Appl. No.:

12/956299

Inventors:

Krishnan Ramani - Cupertino CA, US
Chitresh C. Narasimhaiah - San Jose CA, US
David Hugh McIntyre - Sunnyvale CA, US

Assignee:

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

International Classification:

G06F 9/312

US Classification:

712216, 712E09033

Abstract:

A method and a processor load/store unit (LSU) are described for performing store-to-load forwarding (STLF) from an interlocking store. STLF is performed when a starting address of the store and the load do not match, or when a data size of the store is smaller than a data size of the load. The LSU detects a load that interlocks with a store, and determines whether all or only a portion of data bytes needed by the load can be provided by the interlocking store. If it is determined that only a portion of the data bytes needed by the load can be provided by the interlocking store, then that portion of the data bytes is provided by a store data buffer (SDB) and the remaining portion of the data bytes needed by the load is provided by a data cache (DC). Otherwise, the SDB provides all of the data bytes.