David Anthony Nobles

US Patent:

46202757, Oct 28, 1986

Filed:

Jun 20, 1984

Appl. No.:

6/622451

Inventors:

Steven J. Wallach - Dallas TX
Thomas M. Jones - Dallas TX
Frank J. Marshall - Plano TX
David A. Nobles - Garland TX
Kent A. Fuka - Carrollton TX
Steven M. Rowan - Garland TX
William H. Wallace - Plano TX
Harold W. Dozier - Carrollton TX
David M. Chastain - Plano TX
John W. Clark - Carrollton TX
Robert B. Kolstad - Dallas TX
James E. Mankovich - Plano TX
Michael C. Harris - Bedford TX
Jeffrey H. Gruger - Dallas TX
Alan D. Gant - Garland TX
Harold D. Shelton - Carrollton TX
James R. Weatherford - Lake Dallas TX
Arthur T. Kimmel - Dallas TX
Gary B. Gostin - Coppell TX
Gilbert J. Hansen - Plano TX
John M. Golenbieski - Dallas TX
Larry W. Spry - Dallas TX
Gerald Matulka - Carrollton TX
Gaynel J. Lockhart - Richardson TX
Michael E. Sydow - Carrollton TX

International Classification:

G06F 918

US Classification:

364200

Abstract:

A vector processing computer is configured to operate in a pipelined fashion wherein each of the functional units is essentially independent and is designed to carry out its operational function in the fastest possible manner. Vector elements are transmitted from memory, either main memory, a physical cache unit or a logical cache through a source bus where the elements are alternately loaded into the vector processing units. The vector control unit decodes the vector instructions and generates the required control commands for operating the registers and logical units within the vector processing units. Thus, the vector processing units essentially work in parallel to double the processing rate. The resulting vectors are transmitted through a destination bus to either the physical cache unit, the main memory, the logical cache or to an input/output processor. In a further aspect of the computer there is produced an entry microword from a store for the immediate execution of the first microinstruction within a sequence of microinstructions.

US Patent:

48687421, Sep 19, 1989

Filed:

Jun 9, 1988

Appl. No.:

7/206962

Inventors:

Alan D. Gant - Garland TX
David A. Nobles - Garland TX
Thomas M. Jones - Dallas TX
Arthur T. Kimmel - Dallas TX

Assignee:

Convex Computer Corporation - Richardson TX

International Classification:

G06F 1320
G06F 1342

US Classification:

364200

Abstract:

A communication bus (14) provides bidirectional data communication between a computer (12) and various peripheral units including input/output processors (18, 20) and a service processor (22). The computer includes a memory control unit (24) which is connected to a memory array (26). A central processor unit (30) is connected for data exchange with the memory control unit (24). Data blocks are transferred through the bus (14) and either originate or terminate at the memory array (26). A peripheral unit, such as the processor (18) transfers a data block by first transferring a header parcel (146) which defines an address, block length and type of function. This is transmitted to the memory control unit (24) which carries out the desired data transfer by sending or receiving sequential data parcels. An interrupt bus (16) connects each of the units of the computer system (10) including the processors (18, 20, 22) and the central processing unit (30). Any one of the units connected to the interrupt bus ( 16) can interrupt any of the other units.