Douglas L Anneser

US Patent:

7801699, Sep 21, 2010

Filed:

Apr 10, 2006

Appl. No.:

11/401700

Inventors:

James M. Roucis - Monument CO, US
Robert Chizmadia - Woodbine MD, US
Douglas L. Anneser - Hollis NH, US
Martin C. Shipley - Fort Collins CO, US
Thomas E. Mitchell - Fort Collins CO, US
Martha Johnson - Fort Collins CO, US
Andrew M. Weilert - Fort Collins CO, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA
Avago Technologies General IP (Singapore) Pte. Ltd. - Singapore

International Classification:

G06F 15/00

US Classification:

702182, 716 18, 716 1, 716 4, 714 15, 714 38, 324763, 324765, 438 18, 703 13, 703 14, 703 19

Abstract:

A method for detecting and reporting changes in functional features of a simulation model caused by a software revision is disclosed. In one aspect, the method is independent of simulation model architecture. One performs regression testing with a plurality of feature-specific modules. The feature-specific modules are configured to generate a first set of information with the simulation model and compare the first set of information to a second set of corresponding information from the simulation model. In the above-described testing, the first set of information postdates the software revision and the second set of information predates the software revision.

US Patent:

8271232, Sep 18, 2012

Filed:

Aug 18, 2010

Appl. No.:

12/859223

Inventors:

James M. Roucis - Monument CO, US
Robert Chizmadia - Woodbine MD, US
Douglas L. Anneser - Hollis NH, US
Martin C. Shipley - Fort Collins CO, US
Thomas E. Mitchell - Fort Collins CO, US
Martha Johnson - Fort Collins CO, US
Andrew M. Weilert - Fort Collins CO, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA
Avago Technologies General IP (Singapore) Pte. Ltd. - Singapore

International Classification:

G06F 15/00

US Classification:

702182, 716102, 716 56, 716106, 714 15, 714 37, 714 38, 714E11002, 324763, 324765, 438 18, 703 13, 703 14, 703 19

Abstract:

A method for detecting and reporting changes in functional features of a simulation model caused by a software revision is disclosed. In one aspect, the method is independent of simulation model architecture. One performs regression testing with a plurality of feature-specific modules. The feature-specific modules are configured to generate a first set of information with the simulation model and compare the first set of information to a second set of corresponding information from the simulation model. In the above-described testing, the first set of information postdates the software revision and the second set of information predates the software revision.

US Patent:

54401534, Aug 8, 1995

Filed:

Apr 1, 1994

Appl. No.:

8/222736

Inventors:

Barry J. Male - Nashua NH
Douglas L. Anneser - Chelmsford MA

Assignee:

United Technologies Corporation - Hartford CT

International Classification:

H01L 2970
H01L 27102

US Classification:

257204

Abstract:

A linear, bipolar-type application-specific integrated circuit includes a silicon substrate having a plurality of columns of device primitives or cells. Each cell comprises a plurality of identical NPN and PNP transistors flanking a centrally-located capacitor. Each transistor has dual emitters, bases and collectors. Open field areas are reserved on the silicon substrate on the sides of the columns of cells. Formed in these open field areas are precise thin film silicon chromium resistors. Power planes are also routed in these open field areas. A ground plane is routed in the vicinity of the centrally-located capacitor. Standard analog circuits are personalized using two layers of metallization interconnects.

US Patent:

54123283, May 2, 1995

Filed:

Jun 29, 1994

Appl. No.:

8/267296

Inventors:

Barry J. Male - West Granby CT
Douglas L. Anneser - East Granby CT

Assignee:

United Technologies Corporation - Hartford CT

International Classification:

G01R 3128

US Classification:

324752

Abstract:

The present invention relates to a non-contact current injection apparatus and a method for using the same with linear integrated bipolar circuits. The current injection apparatus has two modes: a calibration mode and an injection mode. The apparatus includes an illumination source for emitting photons toward an electronic component at a desired site for inducing a current in the electronic component. The apparatus further includes a control loop for generating a voltage control signal which causes the illumination source to illuminate to a desired level and a feedback loop which monitors the current induced in the electronic component and compares it or some other end effect to a desired current or end effect. The apparatus also includes a storage device for retaining information about the calibration sequence. The method for using the apparatus broadly comprises calibrating the apparatus using a test array having a series of calibration sites with a target at each site, providing an intensity control signal to the illumination source, illuminating a target at one of the calibration sites, and monitoring the end effect generated in the target by the photon emissions.

US Patent:

55504124, Aug 27, 1996

Filed:

Sep 12, 1994

Appl. No.:

8/304537

Inventors:

Douglas L. Anneser - Hollis NH

Assignee:

United Technologies Corporation - Hartford CT

International Classification:

H01H 4700

US Classification:

307125

Abstract:

A transformer-based electrical circuit that isolates a low voltage level input control signal from a power switching device, such a MOSFET, is disclosed. The circuit includes a pair of complementary dual bipolar transistor configurations connected to the secondary winding of a pulse transformer. The low voltage input signal is connected to the primary winding of the transformer. A pair of resistor network transistor drivers connect to corresponding bipolar transistors, whose outputs connect to the gate terminal of the MOSFET. The drivers are also connected to the complementary transistor pairs. A resistive feedback network is connected between the gate terminal of the MOSFET and the complimentary transistor pairs. The feedback network latches the selected drive voltage to the gate of the MOSFET, thereby keeping it on or off irrespective of the fact that the pulse transformer may have saturated.