Search

Douglas W Barlage

age ~54

from Durham, NC

Get Report
Also known as:
  • Douglas William Barlage
  • Doug W Barlage
  • Douglas W Arlage
  • Douglas W Barlege
  • Douglas W Haqq
Phone and address:
2809 Montcastle Ct, Durham, NC 27705
9194016448
Related to:
Connected to:

Douglas Barlage Phones & Addresses

  • 2809 Montcastle Ct, Durham, NC 27705 • 9194016448 • 9194193468
  • Leipsic, OH
  • Portland, OR
  • 1411 Carlaby Way, Hillsboro, OR 97124
  • Urbana, IL
  • Dayton, OH
  • Champaign, IL
  • 2809 Montcastle Ct, Durham, NC 27705 • 9196415666

Work

  • Position:
    Building and Grounds Cleaning and Maintenance Occupations

Education

  • Degree:
    High school graduate or higher

Emails

d***[email protected]

Us Patents

  • Method For Making A Semiconductor Device Having A High-K Gate Dielectric

    view source
  • US Patent:
    6713358, Mar 30, 2004
  • Filed:
    Nov 5, 2002
  • Appl. No.:
    10/288043
  • Inventors:
    Robert S. Chau - Beaverton OR
    Timothy E. Glassman - Portland OR
    Christopher G. Parker - Portland OR
    Matthew V. Metz - Hillsboro OR
    Lawrence J. Foley - Hillsboro OR
    Reza Arghavani - Aloha OR
    Douglas W. Barlage - Durham NC
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    H01L 21336
  • US Classification:
    438287, 438591
  • Abstract:
    A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate. After forming a silicon nitride layer on the high-k gate dielectric layer, a gate electrode is formed on the silicon nitride layer.

  • Tri-Gate Devices And Methods Of Fabrication

    view source
  • US Patent:
    6858478, Feb 22, 2005
  • Filed:
    Feb 14, 2003
  • Appl. No.:
    10/367263
  • Inventors:
    Robert S. Chau - Beaverton OR, US
    Brian S. Doyle - Portland OR, US
    Jack Kavalieros - Portland OR, US
    Douglas Barlage - Durham NC, US
    Suman Datta - Portland OR, US
    Scott A. Hareland - Tigard OR, US
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    H01L021/00
    H01L021/84
  • US Classification:
    438149, 438157, 438283
  • Abstract:
    The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

  • Tri-Gate Devices And Methods Of Fabrication

    view source
  • US Patent:
    6914295, Jul 5, 2005
  • Filed:
    Jul 8, 2004
  • Appl. No.:
    10/887609
  • Inventors:
    Robert S. Chau - Beaverton OR, US
    Brian S. Doyle - Portland OR, US
    Jack Kavalieros - Portland OR, US
    Douglas Barlage - Durham NC, US
    Suman Datta - Portland OR, US
    Scott A. Hareland - Tigard OR, US
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    H01L029/76
    H01L029/94
  • US Classification:
    257333, 257389, 257395
  • Abstract:
    The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

  • Tri-Gate Devices And Methods Of Fabrication

    view source
  • US Patent:
    7005366, Feb 28, 2006
  • Filed:
    Aug 20, 2004
  • Appl. No.:
    10/923472
  • Inventors:
    Robert S. Chau - Beaverton OR, US
    Brian S. Doyle - Portland OR, US
    Jack Kavalieros - Portland OR, US
    Douglas Barlage - Durham NC, US
    Suman Datta - Portland OR, US
    Scott A. Hareland - Tigard OR, US
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    H01L 21/3205
    H01L 21/4763
  • US Classification:
    438591, 438595
  • Abstract:
    The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

  • Tri-Gate Devices And Methods Of Fabrication

    view source
  • US Patent:
    7358121, Apr 15, 2008
  • Filed:
    Aug 23, 2002
  • Appl. No.:
    10/227068
  • Inventors:
    Robert S. Chau - Beaverton OR, US
    Brian S. Doyle - Portland OR, US
    Jack Kavalieros - Portland OR, US
    Douglas Barlage - Durham NC, US
    Suman Datta - Portland OR, US
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    H01L 21/00
  • US Classification:
    438149, 438197, 438283
  • Abstract:
    The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

  • Tri-Gate Devices And Methods Of Fabrication

    view source
  • US Patent:
    7427794, Sep 23, 2008
  • Filed:
    May 6, 2005
  • Appl. No.:
    11/123565
  • Inventors:
    Robert S. Chau - Beaverton OR, US
    Brian S. Doyle - Portland OR, US
    Jack Kavalieros - Portland OR, US
    Douglas Barlage - Durham NC, US
    Suman Datta - Portland OR, US
    Scott A. Hareland - Tigard OR, US
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    H01L 29/76
    H01L 29/94
  • US Classification:
    257333, 438149, 438283
  • Abstract:
    The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

  • Tri-Gate Devices And Methods Of Fabrication

    view source
  • US Patent:
    7504678, Mar 17, 2009
  • Filed:
    Nov 7, 2003
  • Appl. No.:
    10/703316
  • Inventors:
    Robert S. Chau - Beaverton OR, US
    Brian S. Doyle - Portland OR, US
    Jack Kavalieros - Portland OR, US
    Douglas Barlage - Durham NC, US
    Suman Datta - Portland OR, US
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    H01L 29/80
    H01L 31/112
  • US Classification:
    257287, 257347, 438149
  • Abstract:
    The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

  • Tri-Gate Devices And Methods Of Fabrication

    view source
  • US Patent:
    7514346, Apr 7, 2009
  • Filed:
    Dec 7, 2005
  • Appl. No.:
    11/297084
  • Inventors:
    Robert S. Chau - Beaverton OR, US
    Brian S. Doyle - Portland OR, US
    Jack Kavalieros - Portland OR, US
    Douglas Barlage - Durham NC, US
    Suman Datta - Portland OR, US
    Scott A. Hareland - Tigard OR, US
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    H01L 21/4763
  • US Classification:
    438591, 438149, 257347
  • Abstract:
    The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

Classmates

Douglas Barlage Photo 1

Miller City High School, ...

view source
Graduates:
Doug Barlage (1984-1988),
Helen Lause (1954-1958),
Melissa Rosengarten (1992-1996),
Diane Balbaugh (1971-1975),
Dan Schroeder (2000-2004)

Facebook

Douglas Barlage Photo 2

Douglas William Barlage

view source
Friends:
Emily Barlage Spaulding, Keith Evans, Ginger Wheeler
Get Report for Douglas W Barlage from Durham, NC, age ~54
Control profile