Douglas M Washabaugh

US Patent:

6466997, Oct 15, 2002

Filed:

Jun 14, 1999

Appl. No.:

09/332836

Inventors:

Theodore L. Ross - Maynard MA
Douglas M. Washabaugh - Hubbardston MA
Peter J. Roman - Hopkinton MA
Wing Cheung - Sudbury MA
Koichi Tanaka - Kawasaki, JP
Shinichi Mizuguchi - Kawasaki, JP
Robert E. Thomas - Hudson MA

Assignee:

Enterasys Networks, Inc. - Portsmouth NH

International Classification:

G06F 500

US Classification:

710 48, 714 34

Abstract:

A method and system for requesting an interrupt from a host system to service an adapter connected to the host system and a data interface. Data packets, including one or more data cells, are transferred between the data interface and the host system. The host system includes a host memory that includes a plurality of memory slots to store data packets transferred between the data interface and the host system. It is determined when a transfer of data has resulted in an occurrence of an interrupt event. An interrupt event occurs when the transfer of data includes a transfer of a data cell between the data interface and the host system and the data cell is defined to be an end of a data packet. In response to the occurrence of an interrupt event, it is determined whether to generate an interrupt request to the host system. This step of determining includes determining whether a predetermined interval of time has elapsed since the host system last processed an interrupt request or determining whether a predetermined number of interrupt events have occurred since the host system last processed an interrupt request.

US Patent:

7023856, Apr 4, 2006

Filed:

Jan 24, 2002

Appl. No.:

10/056159

Inventors:

Douglas Markham Washabaugh - Hubbardston MA, US
Thomas Anderson - Hudson NH, US
Kathryn Fuller - North Reading MA, US

Assignee:

Riverstone Networks, Inc. - Santa Clara CA

International Classification:

H04L 12/56

US Classification:

3703951, 370474

Abstract:

Different levels of service are provided to different types of traffic within a single virtual circuit (VC) by converting the traffic from fixed-length cells to variable-length packets, classifying the packets based on information in the packet headers, associating the packets with a VC, and then implementing class-specific enqueuing and dequeuing of the classified packets on a per-VC basis. Classified packets are dequeued from VC-specific and class-specific queues into VC-specific segmentation and re-assembly (SAR) queues according to an algorithm that is a function of traffic class. The dequeuing algorithm determines the level of service that is provided to the different classes of traffic within each VC. Packets are dequeued from the VC-specific SAR queues and converted back to fixed-length cells according to an algorithm that arbitrates among multiple VC-specific SAR queues. The technique for managing traffic can be carried out within an Ethernet switch/router that includes input and output ATM interfaces.

US Patent:

59665467, Oct 12, 1999

Filed:

Sep 12, 1996

Appl. No.:

8/707895

Inventors:

Robert E. Thomas - Hudson MA
Theodore L. Ross - Maynard MA
Douglas M. Washabaugh - Hubbardston MA
Peter J. Roman - Hopkinton MA
Wing Cheung - Sudbury MA
Koichi Tanaka - Kawasaki, JP
Shinichi Mizuguchi - Kawasaki, JP

Assignee:

Cabletron Systems, Inc. - Rochester NH

International Classification:

G06F 1314

US Classification:

395868

Abstract:

A mechanism by which interrupt frequency mitigation is combined with transmit raw cell status report frequency mitigation is presented. A tx raw cell status report is allowed to occur for only every N raw cell tx slots consumed. When the rate of interrupt requests is mitigated in accordance with holdoff parameters including a holdoff event count corresponding to X interrupt events and a holdoff time interval, and the raw cell status report counts as an interrupt event, an interrupt request is generated for an enabled interrupt if N*X events has occurred or the holdoff time interval has elapsed.

US Patent:

61157759, Sep 5, 2000

Filed:

Sep 12, 1996

Appl. No.:

8/712688

Inventors:

Theodore L. Ross - Maynard MA
Douglas M. Washabaugh - Hubbardston MA
Peter J. Roman - Hopkinton MA
Wing Cheung - Sudbury MA
Koichi Tanaka - Kawasaki, JP
Shinichi Mizuguchi - Kawasaki, JP

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1324

US Classification:

710260

Abstract:

A time-based and event-based interrupt frequency mitigation scheme is provided. A holdoff event counter is programmed to count a holdoff event count corresponding to a number of interrupts. A holdoff timer is programmed to time a holdoff interval representing the time period to elapse before the generation of an interrupt request to the host system can occur. When a data transfer request associated with the transfer of data from or to the host system is serviced and results in the occurrence of an interrupt event, the holdoff event counter is modified by one. If either the holdoff event counter or the holdoff timer has expired and the interrupt is enabled, an interrupt request to the host system is generated. In response to such interrupt request generation, the interrupt is processed and both the holdoff event counter and the holdoff timer retriggered.

US Patent:

54045363, Apr 4, 1995

Filed:

Sep 15, 1992

Appl. No.:

7/945198

Inventors:

Kadangode K. Ramakrishnan - Maynard MA
David Sawyer - Merrimac MA
Phillip J. Weeks - Andover MA
Douglas M. Washabaugh - Leominster MA

Assignee:

Digital Equipment Corp. - Maynard MA

International Classification:

G06F 900

US Classification:

395725

Abstract:

Method and apparatus for scheduling operations of a network adapter in such a way as to minimize latency in processing received data packets, while still guaranteeing time for processing necessary background tasks. The method includes executing a polling loop in which repeated tests are made for the presence of receive data to process, but only a limited amount of receive data processing is performed before checking for background processing that needs to be performed. The polling loop ensures that immediate attention is given to processing of receive data, without the inherent latency of interrupt processing, but still gives periodic opportunities for background processing. Background processing is performed for a guaranteed minimum processing time before permitting a return to receive processing. Background processing may be performed without a guaranteed minimum processing time, but only when there is currently no receive processing to do.

US Patent:

62125672, Apr 3, 2001

Filed:

Sep 12, 1996

Appl. No.:

8/712778

Inventors:

Robert E. Thomas - Hudson MA
Douglas M. Washabaugh - Hubbardston MA
Peter J. Roman - Hopkinton MA
Wing Cheung - Sudbury MA

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1516

US Classification:

709231

Abstract:

A mechanism for mitigating the rate at which status reports associated with raw cell data transfers occur during receive operations in a network node is presented. The network node has an adapter for coupling a network and a host system, the host system including a host memory. The adapter operates to reassemble cell data received from the network and store the reassembled cell data in the host memory. A raw report holdoff counter is programmed to count a number corresponding to a preselected rx raw report holdoff value. If a raw cell data transfer request to be processed is detected, rx raw report information necessary to creating an rx raw cell status report is copied to a temporary storage area. When the data is transferred to the host system, the raw report holdoff counter is modified by one. When the modified counter has expired, the rx raw report information is written to a report queue in host memory.

US Patent:

59220465, Jul 13, 1999

Filed:

Sep 12, 1996

Appl. No.:

8/712736

Inventors:

Robert E. Thomas - Hudson MA
Douglas M. Washabaugh - Hubbardston MA
Peter J. Roman - Hopkinton MA
Wing Cheung - Sudbury MA

Assignee:

Cabletron Systems, Inc. - Rochester NH

International Classification:

G06F 1700

US Classification:

709212

Abstract:

A mechanism for avoiding the initiation of control read transactions on a system bus coupling a host system having a host memory and an interface connected to a peripheral unit as data is moved between the host system and the peripheral unit is presented. Control information associated with data memory portions in host memory is written to the interface for data memory portions storing outgoing data and data memory portions to receive incoming data. The interface includes a controller for moving data between the host memory and the interface by first obtaining the control information for the associated data portions. The interface writes status reports in association with the movement of data between the interface and the host memory via the system bus. The mechanism thus enables data transfers to occur via the system without the initiation of control reads in absence of an exception condition.

US Patent:

58622063, Jan 19, 1999

Filed:

Sep 12, 1996

Appl. No.:

8/707894

Inventors:

Robert E. Thomas - Hudson MA
Douglas M. Washabaugh - Hubbardston MA
Peter J. Roman - Hopkinton MA
Wing Cheung - Sudbury MA

Assignee:

Cabletron Systems, Inc. - Rochester NH

International Classification:

H04L 1226

US Classification:

370229

Abstract:

A status report frequency mitigation mechanism for mitigating the frequency of status report generation for raw cells during transmit operations in a network node is presented. The status report frequency mitigation mechanism operates to adjust the frequency with which status reports for raw cells are generated by manipulating the End-of-Packet (EOP) bit in transmit slot descriptors associated with transmit slots containing raw cell data.