A selectable-gain amplifier selectively couples different capacitors and feedback networks to a gain stage to provide operating characteristics that may include constant bandwidth operation. An interpolated VGA includes pairs of gm cells with cross-connected outputs and may include output cascodes. A dual-rank interpolator utilizes a correction current with a second-order temperature characteristic which may compensate for temperature effects in the transistor ranks.
A quadrature demodulator preweights an input signal prior to mixing with in-phase and quadrature clock signals. In an implementation with discrete phase rotation, a series of weighting circuits may be arranged before or after a select circuit to select the amount of phase rotation. Various implementations may include ratioed current mirrors to perform the weighting function, a stacked arrangement of mixers, an H-bridge input stage, integrated mixers and select circuits, and/or selectable gain stages such as gm cells to perform the weighting function.
Differential-Input Single-Supply Variable Gain Amplifier Having Linear-In-Db Gain Control
Barrie Gilbert - Portland OR Eberhard Brunner - Portland OR
Assignee:
Analog Devices
International Classification:
H03G 330
US Classification:
330254
Abstract:
A variable gain amplifier uses a differential attenuator to provide a differential input to which a differential input signal is applied. The differential attenuator is comprised of (N-1). pi. attenuator stages, with each stage forming a pair of attenuator taps for providing an attenuated version of the differential input signal. The differential input forms a high-impedance input, which is essentially floating. Each pair of taps is coupled to the differential inputs of a respective gm stage. The differential outputs of the gm stages are coupled to the differential inputs of a main amplifier, which has a high open-loop gain. The transconductance of each gm stage is controlled by an interpolator which provides a bias current to each of the gm stages in a sequential manner as a gain control voltage is swept from its minimum to its maximum values. The combination of the attenuated input voltage, the varying transconductances produces a gain response that is linear-in-dB relative to the gain control voltage. The output of the main amp is fed back through a gain-setting resistor network through a fixed gm stage.
Barrie Gilbert - Portland OR Daryl Carbonari - Portland OR Eberhard Brunner - Portland OR Fred Weiss - Newberg OR
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H03L 7093 H03L 718
US Classification:
331 14
Abstract:
A charge pump in a phase locked loop is enabled only when a loop filter needs to be updated, thereby reducing the power consumption of the charge pump. The charge pump is enabled or disabled in response to an enable signal which is generated by a latch. The enable signal is activated by look-ahead signals which are activated in advance of either a pulse from a reference signal or a pulse from a variable signal so as to allow the charge pump to stabilize before providing the charge current to update the loop filter. Logic signals from a programmable divider and reference signal generator are used to generate the look-ahead signals. The charge pump is disabled by a reset signal from a phase-frequency detector after the loop filter is updated. The charge pump includes a current switch for generating source and sink charge currents in response to pump-up and pump-down control signals. A bias cell provides two reference signals to the current switch.
Harris Corporation Jan 1989 - Jun 1991
Modem Design Engineer
Analog Devices Jan 1989 - Jun 1991
Senior Design Engineer
Altera Jan 1988 - Aug 1988
Co-Op Applications Engineer
Education:
Oregon Health & Science University 1992 - 1995
Masters, Master of Science In Electrical Engineering, Electrical Engineering, Communications
Santa Clara University 1989 - 1991
Masters, Master of Science In Electrical Engineering, Electrical Engineering, Communications
University of California, Berkeley 1986 - 1988
Bachelors, Bachelor of Science In Electrical Engineering, Electrical Engineering
City College of San Francisco 1983 - 1986
Skills:
Integrated Circuit Design Analog Circuit Design Wireless Microwave Semiconductors Analog Rf Medical Ultrasound Radar Soc Circuit Design Semiconductor Industry Radio Frequency