Eric J Thomsen

US Patent:

49378279, Jun 26, 1990

Filed:

Jul 25, 1989

Appl. No.:

7/385934

Inventors:

Ronald R. Beck - Banks OR
Michael E. Stanbro - Tigard OR
Eric J. Thomsen - Aloha OR

Assignee:

Mentor Graphics Corporation - Beaverton OR

International Classification:

G06F 1100

US Classification:

371 23

Abstract:

A hardware modeling system 10 simulates portions of electrical circuits 16, 18 utilizing actual hardware components in the simulation. Access to these hardware modeling elements 16, 18 is provided on a shared basis to plural workstations 14. Simulation vectors for plural users may be stored discontiguously in a first memory 26 and a single user's vectors are transferred to a second memory 28 for streaming to the elements 16, 18. An optional timing analyzer and memory circuit 34 periodically samples outputs from pins of the hardware modeling elements to provide timing information on the response of such elements. High impedance testing and bus contention detection is performed on the pins of the hardware modeling elements. Clocking signals applied to the hardware modeling elements are adjustable and may be set at extremely high frequencies. A special gating circuit 292 accesses each pin of the hardware modeling elements and incorporates one or more of the above features.

US Patent:

47440848, May 10, 1988

Filed:

Jul 8, 1987

Appl. No.:

7/070598

Inventors:

Ronald R. Beck - Banks OR
Michael E. Stanbro - Tigard OR
Eric J. Thomsen - Aloha OR

Assignee:

Mentor Graphics Corporation - Beaverton OR

International Classification:

G01R 3128
G06F 1100

US Classification:

371 23

Abstract:

A hardware modeling system 10 simulates portions of electrical circuits 16, 18 utilizing actual hardware components in the simulation. Access to these hardware modeling elements 16, 18 is provided on a shared basis to plural workstations 14. Simulation vectors for plural users may be stored discontiguously in a first memory 26 and a single user's vectors are transferred to a second memory 28 for streaming to the elements 16, 18. An optional timing analyzer and memory circuit 34 periodically samples outputs from pins of the hardware modeling elements to provide timing information on the response of such elements. High impedance testing and bus contention detection is performed on the pins of the hardware modeling elements. Clocking signals applied to the hardware modeling elements are adjustable and may be set at extremely high frequencies. A special gating circuit 292 accesses each pin of the hardware modeling elements and incorporates one or more of the above features.

Author:

Eric Thomsen

ISBN #:

0892656999

Author:

Eric Thomsen

ISBN #:

0892657049

Author:

Eric Thomsen

ISBN #:

0892657057

Author:

Eric Thomsen

ISBN #:

0892659645