Intel Corporation since Oct 2008
Product Line Manager for NAND Solutions Group
Intel Jul 2001 - Jun 2008
Senior Process Integration Engineer / California Technology and Manufacturing
Intel Jan 2006 - Jun 2006
Flash Development Failure Analysis Team Manager
Intel Oct 1997 - Jul 2001
Senior Yield Engineer for Portland Technology Development
Xerox Palo Alto Research Center Jun 1991 - Aug 1991
Summer Intern
Education:
Cornell University 1991 - 1997
Ph.D., Applied Physics
Harvard University 1987 - 1991
AB, Physics
Thomas S. Wootton High School 1986 - 1987
Acalanes High School 1983 - 1986
Skills:
Semiconductors Failure Analysis Reliability Intel Manufacturing Team Management Product Management Ssd Semiconductor Failure Analysis Process Integration Testing Yield Ic Semiconductor Industry Flash Memory Design of Experiments Processors Product Development Product Engineering Jmp Silicon Thin Films Cvd Cmos Mems Metrology Device Characterization Lithography Optics Physics Analog Vlsi Characterization Etching Spc R&D Pvd Mixed Signal Photolithography Semiconductor Process Soc Debugging Asic Eda Nanotechnology Materials Science Afm Solar Cells Plasma Etch Cross Functional Team Leadership