Frank M Verdico

age ~46

from Loveland, CO

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Also known as:

Frank Michael Verdico
Joe Verdico

Connected to:

Frank Verdico Phones & Addresses

Loveland, CO
Westminster, CO
Drake, CO
Wiggins, CO
Weldona, CO
Carr, CO
Fairport, NY
Fort Collins, CO
Gilberts, IL

Work

Company:

Intel corporation
Feb 1, 2005 to Mar 2020
Position:

Analog design engineer

Education

Degree:

Bachelors, Bachelor of Science
School / High School:

University of Rochester
1996 to 1999
Specialities:

Electrical Engineering

Skills

Circuit Design • Mixed Signal • Debugging • Analog Circuit Design • Integrated Circuit Design • Semiconductors • Pcie • Perl • Processors • Ic • Creative Problem Solving • Work Well Independently • Perl Script • Scripting • Root Cause Problem Solving • Cpu Design • Io Design • Silicon Debug • High Speed Interfaces • High Speed Digital • Physical Layer • Vlsi • Asic • Verilog • Very Large Scale Integration • Integrated Circuits • Microprocessors • Static Timing Analysis • Computer Architecture • Cmos • Tcl • Integration • Python

Industries

Semiconductors

Resumes

Frank Verdico

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Location:

Loveland, CO

Industry:

Semiconductors

Work:

Intel Corporation Feb 1, 2005 - Mar 2020
Analog Design Engineer
Hewlett-Packard May 1999 - Feb 2005
Design Engineer

Education:

University of Rochester 1996 - 1999
Bachelors, Bachelor of Science, Electrical Engineering

Skills:

Circuit Design
Mixed Signal
Debugging
Analog Circuit Design
Integrated Circuit Design
Semiconductors
Pcie
Perl
Processors
Ic
Creative Problem Solving
Work Well Independently
Perl Script
Scripting
Root Cause Problem Solving
Cpu Design
Io Design
Silicon Debug
High Speed Interfaces
High Speed Digital
Physical Layer
Vlsi
Asic
Verilog
Very Large Scale Integration
Integrated Circuits
Microprocessors
Static Timing Analysis
Computer Architecture
Cmos
Tcl
Integration
Python

Us Patents

Methods And Systems To Write To Soft Error Upset Tolerant Latches
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US Patent:

20100080072, Apr 1, 2010
Filed:

Sep 29, 2008
Appl. No.:

12/240318
Inventors:

Dan Krueger - Fort Collins CO, US
Kevin Duda - Denver CO, US
Frank Verdico - Fort Collins CO, US
International Classification:

G11C 11/416
G11C 29/00
US Classification:

36518916, 365200
Abstract:

Methods and systems to write to redundant storage latches, or storage cells, including soft error upset tolerant latches and feedback-interlocked redundant storage cells, including to write a logic value to one of a plurality of same sense storage nodes, and to write a complementary logic value to a selected one of a plurality of opposite sense storage nodes responsive to the logic value. Remaining storage nodes may be written to through circuitry within the storage cell. Logic values may be output substantially simultaneously with corresponding write operations. A system may include a multiple logic level write circuit to write to the first same sense storage node, and first and second single logic level write circuits to write to the first and second opposite sense storage nodes, respectively.