Frederick W Pew

US Patent:

6745264, Jun 1, 2004

Filed:

Jul 15, 2002

Appl. No.:

10/196106

Inventors:

David Luke - Boise ID
Frederick Pew - Meridian ID
Kris Provencio - Boise ID

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

G06F 9445

US Classification:

710 52, 710 8, 710 22, 710 53, 710104, 710105, 710100, 710305

Abstract:

Hardware Description Language (HDL) code is created for an interface controller so that logic requiring device-specific configuration refers to a parameter file. This set of parameters lets components in a bridge circuit provide support for the same configuration. In another aspect of the invention, a control circuit identifies isochronous endpoints and non-isochronous endpoints. A buffer is configured into a first FIFO mode for isochronous endpoints and configured into a second FIFO mode for non-isochronous endpoints.

US Patent:

6757776, Jun 29, 2004

Filed:

Jul 17, 2002

Appl. No.:

10/198508

Inventors:

Frederick Pew - Meridian ID

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

G06F 900

US Classification:

710310, 710 52, 710 22, 709101, 370252

Abstract:

Embodiments of the invention prevent data from being mishandled at a connected device using a system that verifies that data received after receiving a setup command portion of a control transaction is received without errors and/or without receiving a second setup command used to cancel the first. In some embodiments, a control transaction is processed by receiving a setup token and setup data, setting a predetermined memory location to write the setup data, and then preventing the setup data read from the memory from being acted on until the device verifies that no superceding commands have been received by the device.

US Patent:

6856420, Feb 15, 2005

Filed:

Jul 31, 2000

Appl. No.:

09/631036

Inventors:

Frederick W. Pew - Boise ID, US
Marvin D. Nelson - Meridian ID, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F015/00
G06K001/00
G06K015/02

US Classification:

358 116, 358 117, 711203, 711206, 711209, 710 9, 710110

Abstract:

A printer is described. The printer includes a CPU, a DMA controller and an internal memory. The CPU and the DMA controller are each connected to a first memory bus. The internal memory is connected to a second memory bus. The printer further included an address translation unit connected to both the first and the second memory bus. The address translation operates to receive virtual addresses from both the CPU and the DMA controller over the first memory bus and translates these virtual addresses into physical addresses. The address translation unit transmits the physical addresses to the memory over the second memory bus.

US Patent:

7978357, Jul 12, 2011

Filed:

Jan 30, 2006

Appl. No.:

11/343136

Inventors:

Randall Don Briggs - Boise ID, US
Frederick Walter Pew - Meridian ID, US
Mark David Montierth - Meridian ID, US

Assignee:

Marvell International Technology Ltd.

International Classification:

G06F 3/12

US Classification:

358 115, 358 116

Abstract:

In accordance with the invention, it has been determined that the bandwidth, guaranteed periodic delivery and error correction characteristics of a USB High-Speed Interrupt OUT pipe of the USB 2. 0 standard enable the Interrupt OUT pipe to be used to transfer print data from the host computer to the printer. By using the Interrupt OUT pipe for this purpose, it is no longer necessary to store an entire rasterized page in the formatter memory of the printer before commencing printing of the page. Consequently, the size of the formatter memory device can be relatively small compared to the size of the formatter memory device that is currently used to store an entire rasterized page. Alternatively, the same size memory device as that currently used to store an entire rasterized page may be used to enable higher resolution pages to be printed.