Frederick E Strietelmeier

US Patent:

53882288, Feb 7, 1995

Filed:

May 20, 1993

Appl. No.:

8/065057

Inventors:

Chester A. Heath - Boca Raton FL
James O. Nicholson - Austin TX
James D. Reid - Boynton Beach FL
Frederick E. Strietelmeier - Austin TX

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

G06F 1300

US Classification:

395325

Abstract:

A computer system having a plurality of devices which transmit and receive information over a channel is presented. The system includes, in the preferred embodiment, a central arbitration control circuit and a local arbiter associated with each device contending for channel access. Each local arbiter, corresponding to a device which desires channel access, generates a channel request signal to the central control circuit. At the appropriate time when the channel becomes available, the central control circuit generates an arbitrate signal. All local arbiters, then contending for channel access, compare the priority level on the arbitration bus with the priority value of the device it is arbitrating on behalf of, with the winning device gaining access to the channel. Each of the local arbiters contains a programmable circuit which enables the arbiter to operate either utilizing a linear priority arbitration technique or a fairness priority arbitration technique. Thus, each device is dynamically programmable to operate in a linear mode or a fairness mode depending on user and/or application needs.

US Patent:

51612194, Nov 3, 1992

Filed:

May 31, 1991

Appl. No.:

7/711343

Inventors:

James O. Nicholson - Austin TX
John C. O'Quin - Austin TX
John T. O'Quin - Austin TX
Frederick E. Strietelmeier - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200
G06F 1300

US Classification:

395425

Abstract:

A computer system has a cache located between input/output devices and a main system memory. All system memory accesses by the input/output devices are made through the cache. Memory accesses through the cache are limited to those addresses which are accessible to a central processor and input/output devices. All access to such addresses by the central processor are made through the cache.

US Patent:

52936228, Mar 8, 1994

Filed:

Jul 24, 1992

Appl. No.:

7/919817

Inventors:

James O. Nicholson - Austin TX
John C. O'Quin - Austin TX
John T. O'Quin - Austin TX
Frederick E. Strietelmeier - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1202
G06F 1300

US Classification:

395425

Abstract:

A computer system has a cache located between input/output devices and a main system memory. All system memory accesses by the input/output devices are made through the cache. Memory accesses through the cache are limited to those addresses which are accessible to a central processor and input/output devices. All access to such addresses by the central processor are made through the cache.

US Patent:

55069720, Apr 9, 1996

Filed:

Sep 29, 1994

Appl. No.:

8/315167

Inventors:

Chester A. Heath - Boca Raton FL
James O. Nicholson - Austin TX
James D. Reid - Boynton Beach FL
Frederick E. Strietelmeier - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1336

US Classification:

395293

Abstract:

A computer system having a plurality of devices which transmit and receive information over a channel is presented. The system includes, in the preferred embodiment, a central arbitration control circuit and a local arbiter associated with each device contending for channel access. Each local arbiter, corresponding to a device which desires channel access, generates a channel request signal to the central control circuit. At the appropriate time when the channel becomes available, the central control circuit generates an arbitrate signal. All local arbiters, then contending for channel access, compare the priority level on the arbitration bus with the priority value of the device it is arbitrating on behalf of, with the winning device gaining access to the channel. Each of the local arbiters contains a programmable circuit which enables the arbiter to operate either utilizing a linear priority arbitration technique or a fairness priority arbitration technique. Thus, each device is dynamically programmable to operate in a linear mode or a fairness mode depending on user and/or application needs.