Gale A Sill

US Patent:

6675362, Jan 6, 2004

Filed:

Jun 12, 2000

Appl. No.:

09/592033

Inventors:

Richard D. Ortiz - Roseville CA
John P. Huetter - Auburn CA
Gale A. Sill - Roseville CA
Duong Xuan Vu - Antelope CA

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

G06F 1750

US Classification:

716 4, 716 1

Abstract:

Methods and apparatus for managing circuit tests. In a first embodiment of the invention, a number of electrical characteristics of a number of electrical components which exist in a circuit are identified, and the number of electrical components are then grouped in response to the number of electrical characteristics. Thereafter, and for each group of electrical components, a circuit test which is common to the electrical components of the group is established. When the execution of a test results in a false fail, the test is debugged, and the debugged test is then associated with each other component in its group. Much of a programmers debug effort is therefore âproactiveâ rather than âreactiveâ. Preferably, a test history log is maintained for each component group so that previously abandoned test solutions are not repeated as tests are debugged. In a second embodiment of the invention, a number of test parameters of a number of circuit tests created for a number of electrical components which exist in a circuit are identified.