Gang Ji
from Santa Clara, CA
- Also known as:
-
- Ji Jang
Gang Ji Phones & Addresses
- 2389 Homestead Rd, Santa Clara, CA 95050 • 5036174835
- 126 Elm St, San Mateo, CA 94401
- 18710 Rock Creek Rd, Portland, OR 97229 • 5036174835
- 1317 Spring St, Madison, WI 53715 • 6082557326
- 30 S Chapel Ave #C, Alhambra, CA 91801
- 2389 Homestead Rd, Santa Clara, CA 95050
Work
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Company:Intel corporation, pccg, csa, platform power architectureAug 2012 to Aug 2013
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Address:Santa Clara, CA
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Position:Engineering manager of display, power source, and enabling (dpse)
Education
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Degree:MS
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School / High School:University of Wisconsin-Madison1997 to 1998
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Specialities:ECE
Skills
Testing • Hardware • Signal Integrity • Semiconductors • Computer Architecture • Analog • Electrical Engineering • Hardware Architecture • Battery Management Systems • Power Delivery • Mixed Signal • Electronics Packaging • Customer Engagement • Supplier Development • Batteries • Team Building • Technology Management • Innovation Management • Technological Innovation • Collaboration • Computer Hardware
Languages
Chinese
Awards
Intel achievement award - Intel
Emails
Industries
Computer Hardware
Name / Title
Company / Classification
Phones & Addresses
Ruggedura Technology, LLC
Information Technology Consulting Servic · Nonclassifiable Establishments
Information Technology Consulting Servic · Nonclassifiable Establishments
2389 Homestead Rd, Santa Clara, CA 95050
Resumes
Manager Of Display, Power Source, And Enabling Function At Intel Corporation
view sourcePosition:
Engineering Manager of Display, Power Source, and Enabling (DPSE) at Intel Corporation, PCCG, CSA, Platform Power Architecture
Location:
San Francisco Bay Area
Industry:
Computer Hardware
Work:
Intel Corporation, PCCG, CSA, Platform Power Architecture - Santa Clara, CA since Aug 2012
Engineering Manager of Display, Power Source, and Enabling (DPSE)
Intel Corporation - Santa Clara, CA Sep 2010 - Aug 2012
Technical Lead, Battery Engineering
Intel / mobile platform group - Santa Clara, CA Mar 2005 - Sep 2010
Technical Lead, Hardware Engineer
Intel / microprocessor design group - Hillsboro, OR May 1999 - Mar 2005
Sr. Componenet Design Engineer
Engineering Manager of Display, Power Source, and Enabling (DPSE)
Intel Corporation - Santa Clara, CA Sep 2010 - Aug 2012
Technical Lead, Battery Engineering
Intel / mobile platform group - Santa Clara, CA Mar 2005 - Sep 2010
Technical Lead, Hardware Engineer
Intel / microprocessor design group - Hillsboro, OR May 1999 - Mar 2005
Sr. Componenet Design Engineer
Education:
University of Wisconsin-Madison 1997 - 1998
MS, ECE National Taiwan University 1991 - 1995
BS, EE
MS, ECE National Taiwan University 1991 - 1995
BS, EE
Skills:
Testing
Hardware
Signal Integrity
Semiconductors
Computer Architecture
Analog
Electrical Engineering
Hardware Architecture
Battery Management Systems
Power Delivery
Mixed Signal
Electronics Packaging
Customer Engagement
Supplier Development
Batteries
Team Building
Technology Management
Innovation Management
Technological Innovation
Collaboration
Computer Hardware
Hardware
Signal Integrity
Semiconductors
Computer Architecture
Analog
Electrical Engineering
Hardware Architecture
Battery Management Systems
Power Delivery
Mixed Signal
Electronics Packaging
Customer Engagement
Supplier Development
Batteries
Team Building
Technology Management
Innovation Management
Technological Innovation
Collaboration
Computer Hardware
Honor & Awards:
Intel Achievement Award 2002, the highest Intel award, for developing innovate methodology for power delivery optimization on microprocessor which resulted in the cost-effective strategy to achieve optimal package level decoupling.
Languages:
Chinese
Awards:
Intel Achievement Award
Intel
Intel
Plaxo
Gang Ji
view sourceContracts Manager at Perini Building Company
Googleplus
Gang Ji
Gang Ji
Gang Ji
Gang Ji
Education:
广州市东环中学
Gang Ji
Flickr
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