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Girish A Dixit

age ~63

from San Jose, CA

Also known as:
  • Girish Anant Dixit
  • Girish S Dixit
  • Girsh A Dixit
  • Sarojini G Dixit
  • Dixit Girsh
Phone and address:
3258 Reserve Ct, San Jose, CA 95135
4082232009

Girish Dixit Phones & Addresses

  • 3258 Reserve Ct, San Jose, CA 95135 • 4082232009
  • 3133 Hoffman Dr, Plano, TX 75025 • 9726187537
  • Dallas, TX
  • Austin, TX

Work

  • Position:
    Professional/Technical

Us Patents

  • Metallization Structure, And Associated Method, To Improve Crystallographic Texture And Cavity Fill For Cvd Aluminum/Pvd Aluminum Alloy Films

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  • US Patent:
    6355558, Mar 12, 2002
  • Filed:
    Jun 10, 1999
  • Appl. No.:
    09/332362
  • Inventors:
    Girish Dixit - Plano TX
    Anthony Konecni - Plano TX
  • Assignee:
    Texas Instruments Incorporated - Dallas TX
  • International Classification:
    H01L 2144
  • US Classification:
    438642, 438680, 438677, 438648
  • Abstract:
    A metallization structure, and associated method, for filling contact and via apertures to significantly reduce the occurrence of microvoids and provide desirable grain orientation and texture. A modified barrier structure is set forth for contact apertures, and a modified liner structure is set forth for via apertures. The metallization fill structure for contact apertures includes a first wetting or glue layer of refractory metal on the contact aperture, a layer of TiN on the first wetting layer, a second wetting layer of plasma-treated refractory metal on the barrier layer, a layer of CVD Al on the second wetting refractory metal layer, and a PVD Al alloy to fill the contact aperture. The fill structure for via apertures includes an initial plasma-treated refractory metal liner deposited on the via aperture. A CVD Al liner is positioned on the initial refractory metal liner. A PVD Al alloy layer is positioned on the CVD Al liner to fill the via aperture.
  • Passivation Of Inlaid Metallization

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  • US Patent:
    6355559, Mar 12, 2002
  • Filed:
    Nov 3, 2000
  • Appl. No.:
    09/706275
  • Inventors:
    Robert H. Havemann - Garland TX
    Girish Dixit - San Jose CA
  • Assignee:
    Texas Instruments Incorporated - Dallas TX
  • International Classification:
    H01L 214763
  • US Classification:
    438643, 438687, 438653, 438627
  • Abstract:
    A method for forming a metal interconnect having a self-aligned transition metal-nitride barrier ( ). After the metal interconnect lines ( ) are formed, a transition metal ( ) is deposited over the surface of the metal interconnect lines ( ) and reacted in to form a metal-compound ( ). The metal-compound ( ) is then annealed in a nitrogen ambient to form a barrier layer ( ) at the surface of the metal interconnect lines ( ).
  • Integrated Circuit Interconnect And Method

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  • US Patent:
    6358849, Mar 19, 2002
  • Filed:
    Dec 21, 1999
  • Appl. No.:
    09/467680
  • Inventors:
    Robert H. Havemann - Garland TX
    Girish A. Dixit - San Jose CA
    Manoj Jain - Plano TX
    Eden Zielinski - Boise ID
    Jeffrey West - San Antonio TX
  • Assignee:
    Texas Instruments Incorporated - Dallas TX
  • International Classification:
    H01L 21302
  • US Classification:
    438689, 438700, 438723, 438724
  • Abstract:
    A dual inlaid interconnect fabrication method using a temporary filler in a via during trench etch and removal of the filler after trench etch. This provides via bottom protection during trench etch.
  • Vault Shaped Target And Magnetron Operable In Two Sputtering Modes

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  • US Patent:
    6451177, Sep 17, 2002
  • Filed:
    Nov 1, 2000
  • Appl. No.:
    09/703601
  • Inventors:
    Praburam Gopalraja - Sunnyvale CA
    Jianming Fu - San Jose CA
    Fusen Chen - Saratoga CA
    Girish Dixit - San Jose CA
    Zheng Xu - Foster City CA
    Wei Wang - Santa Clara CA
    Ashok K. Sinha - Palo Alto CA
  • Assignee:
    Applied Materials, Inc. - Santa Clara CA
  • International Classification:
    C23C 1435
  • US Classification:
    20419212, 2042982, 20429822, 20429812, 205205
  • Abstract:
    A target and magnetron for a plasma sputter reactor. The target has an annular vault facing the wafer to be sputter coated. Various types of magnetic means positioned around the vault create a magnetic field supporting a plasma extending over a large volume of the vault. Preferably, the magnetron includes annular magnets of opposed polarities disposed behind the two vault sidewalls and a small closed unbalanced magnetron of nested magnets of opposed polarities scanned along the vault roof. An integrated copper via filling process with the inventive reactor or other reactor includes a first step of highly ionized sputter deposition of copper, which can optionally be used to remove the barrier layer at the bottom of the via, a second step of more neutral, lower-energy sputter deposition of copper to complete the seed layer, and a third step of electroplating copper into the hole to complete the metallization. The first two steps can be also used with barrier metals.
  • Integrated Copper Fill Process

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  • US Patent:
    6485618, Nov 26, 2002
  • Filed:
    Jul 30, 2001
  • Appl. No.:
    09/917985
  • Inventors:
    Praburam Gopalraja - Sunnyvale CA
    Jianming Fu - San Jose CA
    Fusen Chen - Saratoga CA
    Girish Dixit - San Jose CA
    Zheng Xu - Foster City CA
    Sankaram Athreya - Sunnyvale CA
    Wei D. Wang - Santa Clara CA
    Ashok K. Sinha - Palo Alto CA
  • Assignee:
    Applied Materials, Inc. - Santa Clara CA
  • International Classification:
    C23C 1434
  • US Classification:
    20419217, 20419215, 20419232, 20419235, 20419212, 438675, 438678, 438687, 205205, 205215, 427588
  • Abstract:
    A target and magnetron for a plasma sputter reactor. The target has an annular vault facing the wafer to be sputter coated. Various types of magnetic means positioned around the vault create a magnetic field supporting a plasma extending over a large volume of the vault. An integrated copper via filling process includes a first step of highly ionized sputter deposition of copper, a second step of more neutral, lower-energy sputter deposition of copper to complete the seed layer, and electroplating copper into the hole to complete the metallization.
  • Bi-Layer Etch Stop For Inter-Level Via

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  • US Patent:
    6566258, May 20, 2003
  • Filed:
    May 10, 2000
  • Appl. No.:
    09/568620
  • Inventors:
    Girish A. Dixit - San Jose CA
    Fusen Chen - Saratoga CA
  • Assignee:
    Applied Materials, Inc. - Santa Clara CA
  • International Classification:
    H01L 21302
  • US Classification:
    438687, 438692, 438723, 438724, 438740, 438750, 438704, 438734
  • Abstract:
    An inter-level metallization structure and the method of forming it, preferably based on copper dual damascene in which the lower-metal level is formed with a exposed metallization and an adjacent, embedded stop layer, both the metallization and embedded stop layer have exposed surfaces approximately level with each other with a lower dielectric layer. The upper-metal level includes a second stop layer deposited over the embedded stop layer and the first metallization and a second dielectric layer. An inter-level via is etched through the second dielectric layer and through the second stop layer and metal is filled into the via to contact the metallization. If the inter-level via is offset over the edge of the metallization, the metal in the via contacts the embedded stop layer and not the first dielectric layer, whereby the embedded stop layer acts as a copper diffusion barrier. The structure and method are particularly useful when the sidewalls of via hole are first coated with a second copper barrier layer but the via bottom is not so coated, thereby decreasing contact resistance and allowing copper diffusion in the absence of an in-line barrier.
  • Self Aligning Non Contact Shadow Ring Process Kit

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  • US Patent:
    6589352, Jul 8, 2003
  • Filed:
    Dec 10, 1999
  • Appl. No.:
    09/459313
  • Inventors:
    Joseph Yudovsky - Campbell CA
    Lawrence C. Lei - Milpitas CA
    Salvador Umotoy - Antioch CA
    Tom Madar - Sunnyvale CA
    Girish Dixit - San Jose CA
  • Assignee:
    Applied Materials, Inc. - Santa Clara CA
  • International Classification:
    C23C 1600
  • US Classification:
    118729, 118720, 118728, 118500, 1563453, 15634551, 15634554, 20429811, 20429815
  • Abstract:
    The invention provides a removable first edge ring configured for pin and recess/slot coupling with a second edge ring disposed on the substrate support. In one embodiment, a first edge ring includes a plurality of pins, and a second edge ring includes one or more alignment recesses and one or more alignment slots for mating engagement with the pins. Each of the alignment recesses and alignment slots are at least as wide as the corresponding pins, and each of the alignment slots extends in the radial direction a length that is sufficient to compensate for the difference in thermal expansion between the first edge ring and the second edge ring.
  • Low Pressure, Low Temperature, Semiconductor Gap Filling Process

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  • US Patent:
    6589865, Jul 8, 2003
  • Filed:
    Jul 6, 2001
  • Appl. No.:
    09/899194
  • Inventors:
    Girish A. Dixit - Plano TX
    Anthony Konecni - Plano TX
    Robert H. Havemann - Garland TX
  • Assignee:
    Texas Instruments Incorporated - Dallas TX
  • International Classification:
    H01L 214763
  • US Classification:
    438637, 438474, 438475, 438629, 438639, 438672, 438674, 438675, 438680
  • Abstract:
    A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures of no more than about 300Â C. , and preferably between about 20Â-275Â C. , which temperature range permits for the use of low dielectric constant ( ) polymers (i. e. , 3. 0). Preferably, the cavities are provided with an elemental titanium-free liner to facilitate cavity filling, and the cavities are filled with CVD aluminum that is introduced into the cavities by way of a forcefill at pressures ranging from atmospheric to about 50 MPa, and preferably no more than about 30 MPa, at temperatures ranging from about 100Â-300Â C. Cavities filled in the foregoing manner exhibit electrical resistance levels that are up to 30% less than structures filled by conventional practices.

Resumes

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Practitioner, Trainer

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Heartfulness Institute
Practitioner, Trainer

Novellus Systems
Vice President, Customer Integration Center
Skills:
Cross Functional Team Leadership
Semiconductor Industry
Semiconductors
Product Management
Thin Films
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Other Social Networks

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girish dixit Google+

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GooglePlus
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Googleplus

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Youtube

Hi Porgi Konachi

Hi Porgi Konachi - Marathi Movie - 2008 - Featuring Nirmiti Sawant, Ar...

  • Category:
    Movies
  • Uploaded:
    30 Sep, 2010
  • Duration:
    2h 10m 18s

Kon Halave Limbdi

A brother-sister song from the Gujarati movie "Sonbai ni Chundadi" Mov...

  • Category:
    Music
  • Uploaded:
    26 Jan, 2011
  • Duration:
    2m 43s

Sheesha Ho Ya Dil Ho - Aasha ( 720p HD Song )

Hindi song : Sheesha Ho Ya Dil Ho Hindi Film : Aasha Directed by J. Om...

  • Category:
    People & Blogs
  • Uploaded:
    12 Oct, 2010
  • Duration:
    2m 44s

Girish Dixit, HDFC Bank, discusses the key ri...

Girish Dixit, Head-Cyber Defense, HDFC Bank, emphasises the changing t...

  • Duration:
    5m 49s

Let's talk about Dil Chahta Hai (2001) | Giri...

Let's talk about Dil Chahta Hai (2001). Dil Chahta Hai is a coming-of-...

  • Duration:
    9m 30s

Don't Judge a Book By It's Cover | Desi Peopl...

" Do not Judge a Book By It's Cover " this video is about Trust Do fol...

  • Duration:
    11m 40s

Girish Dixit actour

Music dance acting singing.

  • Duration:
    2m 18s

NIRMAYEE DIXIT ON SAHARA SAMAY MUMBAI.asf

in ssc exam-2011 nirmayee girish dixit got 95.09 percent marks, sahara...

  • Category:
    News & Politics
  • Uploaded:
    19 Jun, 2011
  • Duration:
    15m 10s

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