Gregory J Grula

US Patent:

51751224, Dec 29, 1992

Filed:

Jun 28, 1991

Appl. No.:

7/723209

Inventors:

Ching-Tai S. Wang - Worcester MA
Gregory J. Grula - Charlton MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

H01L 2176

US Classification:

437 67

Abstract:

A method of planarizing the surface of a silicon wafer of the type employing trench isolation is disclosed where the trenches and active areas of wafer surface may be of varying widths. The trenches and active areas are covered with a conformal coating of silicon oxide, and, according to one embodiment, this coating is subjected to an etch to leave sidewall spacers of oxide at the sidewalls of the trenches, then a second conformal coating of oxide is applied. A first layer of photoresist is applied to the face and patterned to leave photoresist only in the wider trenches. According to another embodiment the remaining photoresist of the first layer is reflowed by a heat treatment to account for any misalignment or the like. A second layer of photoresist is applied, then etched back to the conformal coating on the active areas, leaving some resist in narrow trenches. A third layer of photoresist is applied and then the three layers of photoresist plus oxide are simultaneously etched back to the level of the tops of the active areas, leaving a substantially planar surface where there is a minimum of variation in height in the various areas of differing trench and active area widths.

US Patent:

52963926, Mar 22, 1994

Filed:

Feb 24, 1992

Appl. No.:

7/841239

Inventors:

Gregory J. Grula - Charlton MA
Walter C. Metz - Shrewsbury MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

H01L 21225
H01L 21302

US Classification:

437 34

Abstract:

In a semiconductor substrate, a method of forming a shallow isolation trench having a doped sidewall is disclosed. A shallow trench having nearly vertical walls is formed in the semiconductor substrate. A doped silicon layer is selectively grown on a sidewall and a portion of the bottom of the trench. The dopant from the silicon layer is then driven into the substrate by a suitable method such as annealing. The trench is subsequently filled with a dielectric material.

US Patent:

60603879, May 9, 2000

Filed:

Nov 20, 1995

Appl. No.:

8/574557

Inventors:

Adam Shepela - Bolton MA
Gregory J. Grula - Charlton MA
Bjorn Zetterlund - Marlborough MA

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

H01L 214763

US Classification:

438630

Abstract:

A new process for creating a transistor in an integrated circuit provides for two suicide formations, each independent of the other, from two metal depositions and formations steps. The process produces a sufficiently low resistance silicide layer over the source/drain region surfaces of the transistor while also creating a lower resistance silicide over the gate interconnects. In an example embodiment of the invention a near-planar isolation process is used applied such that the gate interconnect surfaces are co-planar. A first silicide layer is formed over the source/drain regions. A dielectric gap-fill material is applied. A planarization method such as chemical mechanical polishing is used to remove the gap fill material down to the top surface of the gate interconnect. A relatively thick suicide is then formed over the top surface of the gate interconnect.

US Patent:

50772341, Dec 31, 1991

Filed:

Jun 29, 1990

Appl. No.:

7/545858

Inventors:

John P. Scoopo - Austin TX
Frances P. Alvarez - Medfield MA
Gregory J. Grula - Charlton MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

H01L 2176
H01L 21312

US Classification:

437 67

Abstract:

A planarization method utilizing three resist layers is disclosed. In a substrate where the surface geometry contains trenches or steps of constant height separated by varying distances, after a CVD oxidation layer is formed, a first resist layer (plugs) is formed in wide trenches. A second resist layer is formed on the substrate to provide a gross global planarization of the substrate, which is etched back until all of the resist is removed from the active areas. A third resist layer is then formed on the substrate to provide a near planar surface. All of the resist and CVD oxide is removed from the active areas.