Hirotsugu Kojima

US Patent:

55193986, May 21, 1996

Filed:

Oct 13, 1993

Appl. No.:

8/135478

Inventors:

Naoki Satoh - Kokubunji, JP
Hirotsugu Kojima - Foster City CA
Hideki Sawaguchi - Kodaira, JP
Masao Hotta - Hanno, JP

Assignee:

Hitachi, Ltd. - Tokyo

International Classification:

H03M 136

US Classification:

341159

Abstract:

A signal processing apparatus for converting an analog signal to a digital signal and processing the digital signal. In particular, a digital filter for performing processing at high speed is implemented by using an integrated circuit of low power consumption. The signal processing apparatus includes a circuit for comparing an input analog signal with each voltage of a plurality of analog reference voltages and generating a thermometer code Tc depending upon the analog input signal, a decoder for detecting a change point of the thermometer code Tc, and a plurality of memory circuits having output signal lines of the decoder as word selection lines. The product of an input signal value corresponding to each word selection line and a predetermined filter coefficient is stored in the corresponding word of the memory circuits. The memories are used as look-up tables.

US Patent:

58809813, Mar 9, 1999

Filed:

Aug 12, 1996

Appl. No.:

8/695617

Inventors:

Hirotsugu Kojima - Foster City CA
Avadhani Shridhar - Sunnyvale CA

Assignee:

Hitachi America, Ltd. - NY

International Classification:

G06F 738
G06F 752

US Classification:

36473602

Abstract:

The present invention contemplates an improved multiplier circuit and method for reducing power consumption by reducing the number of transitions to the input of the multiplier. Each input to the multiplier is fixed for as long as possible by reordering the sequence of the multiplications to take advantage of duplicate input values. The intermediate results of each multiplication are stored in separate accumulators to obtain the final resultants. Power consumption is further reduced through a reduction in the number of transitions on the data bus linking the multiplier and the data register file containing the accumulators.

US Patent:

56873824, Nov 11, 1997

Filed:

Jun 7, 1995

Appl. No.:

8/473761

Inventors:

Hirotsugu Kojima - Foster City CA
Katsuro Sasaki - Los Altos CA

Assignee:

Hitachi America, Ltd. - Tarrytown NY

International Classification:

G06F 132
G11C 1140

US Classification:

395750

Abstract:

A memory system including a first memory area (MEM-A) implemented using memory units including low threshold voltage transistors powered by a low supply voltage source, and a second memory area (MEM-B) implemented using memory units including higher threshold voltage cells powered by a higher supply voltage source. The first memory area, MEM-A, is designated to contain frequently accessed variables, with less frequently accessed variables designated for storage in the second memory area, MEM-B. The most frequently accessed variables stored in MEM-A provide for fast access at a low power per access power dissipation level due to the lower supply voltage and lower threshold voltage design. Alternatively, the less frequently accessed variables stored in MEM-B require a high power per access, but negligible leakage current during static steady state conditions.

US Patent:

59664070, Oct 12, 1999

Filed:

May 31, 1994

Appl. No.:

8/251185

Inventors:

Mitsuru Hiraki - Hachioji, JP
Hirotsugu Kojima - Foster City CA
Masaru Kokubo - Hanno, JP
Takafumi Kikuchi - Kokubunji, JP
Yuji Hatano - Kodaira, JP
Kouki Noguchi - Kokubunji, JP
Masao Hotta - Hanno, JP

Assignee:

Hitachi, Ltd. - Tokyo

International Classification:

H04B 300
H04B 2500

US Classification:

375257

Abstract:

A bus driving system includes n bus wires having data signal wires and control signal wires, (n-1) switching circuits constituting driver circuits at a transmitting end, a precharge circuitry for precharging (n-2) bus wires and (n-1)-th bus wire with a control circuit for redistributing wire capacitances of transmission lines formed by the bus wires, and a predischarge circuitry for predischarging n-th bus wire. The switching circuits control conduction and non-conduction between (n-2) bus wires, (n-1)-th bus wire and n-th bus wire, wherein the (n-2) switching circuits respond to (n-2) bit signals and a control signal, while the (n-1)-th switching circuit responds to the control signal. The signal from the transmitting end is detected by a detection circuit at a receiving end via the transmission lines.