Hoon Ryu

US Patent:

7573769, Aug 11, 2009

Filed:

Jan 3, 2008

Appl. No.:

11/968969

Inventors:

Hoon Ryu - Cary NC, US

Assignee:

Qimonda North America Corp. - Cary NC

International Classification:

G11C 11/4091

US Classification:

365212, 3652335, 365208, 365194, 365196, 365195, 365190, 327288, 327285, 327281, 327278

Abstract:

A sense amplifier enable signal generator has two stages. Each stage offsets transistor performance variation in the other stage to produce an enable signal output relatively immune from the effects associated with transistor mismatches. In one embodiment, a memory device comprises a plurality of memory cells, sense amplifier circuitry and the enable signal generator. The sense amplifier circuitry is coupled to one or more of the memory cells and senses the state of the one or more memory cells when enabled. The enable signal generator has first and second stages and generates an enable signal applied to the sense amplifier circuitry. The enable signal generator counteracts delay variation when generating the enable signal so that operation of the enable signal generator is substantially unaffected by transistor performance variation in either stage of the enable signal generator.

US Patent:

7684273, Mar 23, 2010

Filed:

Nov 14, 2007

Appl. No.:

11/939903

Inventors:

Hoon Ryu - Cary NC, US

Assignee:

Qimonda North America Corp. - Cary NC

International Classification:

G11C 7/02

US Classification:

365207, 365205, 365148

Abstract:

A memory device includes sense amplifier circuitry, a current sink and a resistive element. The sense amplifier circuitry is operable to evaluate data read from a memory array included in the memory device responsive to a bias voltage applied to the sense amplifier circuitry. The current sink is operable to sink a bias current. The resistive element couples the current sink to the sense amplifier circuitry. The bias voltage applied to the sense amplifier circuitry corresponds to the voltage drop across the resistive element and current sink as induced by the bias current.

US Patent:

7802133, Sep 21, 2010

Filed:

Jun 29, 2007

Appl. No.:

11/819759

Inventors:

KoonHee Lee - South Burlington VT, US
Ryan Patterson - Burlington VT, US
Hoon Ryu - Cary NC, US
Klaus Nierle - Essex Junction VT, US

Assignee:

Qimonda North America Corp. - Durham NC

International Classification:

G06F 11/00

US Classification:

714 8, 714710

Abstract:

A multiple-chip memory device, comprising: a volatile memory element configured to store a plurality of bits of information, and later access the plurality of bits of information; a non-volatile memory element configured to store initial repair information identifying one or more errors in the volatile memory element; and a master memory controller configured to read the initial repair information, and to provide processed repair information and volatile memory control signals to the volatile memory element, wherein the volatile memory element is configured to store and access the plurality of bits of information based on the processed repair information and logical address information.

US Patent:

7843746, Nov 30, 2010

Filed:

Dec 31, 2007

Appl. No.:

12/003701

Inventors:

Hoon Ryu - Cary NC, US

Assignee:

Qimonda AG - München

International Classification:

G11C 29/00
G11C 7/00

US Classification:

365200, 714710, 714711

Abstract:

A redundancy replacement scheme for a semiconductor device repairing a faulty memory cell in a column select line group with a spare memory cell in the column select line group based on a physical or logical address of the selected row.

US Patent:

8468401, Jun 18, 2013

Filed:

Aug 13, 2010

Appl. No.:

12/856225

Inventors:

KoonHee Lee - South Burlington VT, US
Ryan Patterson - Burlington VT, US
Hoon Ryu - Cary NC, US
Klaus Nierle - Essex Junction VT, US

Assignee:

Qimonda AG - Munich

International Classification:

G06F 11/00

US Classification:

714723, 438 15

Abstract:

A method for manufacturing a multiple-chip memory device includes making a volatile memory element on a semiconductor substrate, examining the volatile memory element for one or more initial errors, correcting the one or more initial errors on the semiconductor substrate, incorporating the volatile memory element into the multiple-chip memory device, and incorporating a non-volatile memory element into the multiple-chip memory device. The volatile memory element is examined for one or more secondary errors, after incorporating the volatile memory element and the non-volatile memory element into the multiple-chip memory device. Repair information is stored in a non-volatile memory element, the repair information identifying the one or more secondary errors.

US Patent:

20100070676, Mar 18, 2010

Filed:

Sep 12, 2008

Appl. No.:

12/209542

Inventors:

Hoon Ryu - Cary NC, US

Assignee:

Qimonda North America Corporation - Cary NC

International Classification:

G06F 12/06

US Classification:

711 5, 711E12082

Abstract:

In one embodiment, a memory device comprises a plurality of memory banks. At least two of the memory banks share the same bus. Logic is coupled to the memory banks via the different buses. The logic controls access to the memory banks. A bi-directional tri-state buffer is interposed between adjacent memory banks along the same bus so that each bus is segmented into a plurality of sections, each bus section being coupled to one or more different ones of the memory banks.

US Patent:

20200228739, Jul 16, 2020

Filed:

Jan 14, 2019

Appl. No.:

16/247475

Inventors:

- Santa Clara CA, US
Hoon RYU - Sunnyvale CA, US
Taehyung JUNG - Santa Clara CA, US

International Classification:

H04N 5/378
H04N 5/3745
H04N 5/369

Abstract:

An image sensor has an array of pixels configured in multiple blocks; each block coupled to a separate analog-to-digital converter (ADC) to provide digitized image data. The ADCs feed digitized images into an image RAM; and the image RAM feeds digitized images to an alignment buffer in a first pixel order. The alignment buffer provides digitized images to an image processor in a second pixel order different from the first pixel order. In an embodiment, the alignment buffer uses a multiport RAM. In another embodiment, the alignment buffer uses first and second alignment buffer RAMs, writing one alignment buffer RAM while reading the other alignment buffer RAM to provide image data to the image processor. In embodiments, the alignment buffer provides digitized images in an order selectable between a full resolution and a reduced resolution order, and selectable between a right-to-left and left-to-right order.

US Patent:

20200092509, Mar 19, 2020

Filed:

Sep 17, 2018

Appl. No.:

16/133449

Inventors:

- Santa Clara CA, US
Hoon RYU - Sunnyvale CA, US
Zheng YANG - San Jose CA, US
Hyunsu YOON - San Jose CA, US
Chia-Ming CHEN - San Jose CA, US

International Classification:

H04N 5/3745

Abstract:

A multiple IC, buffered, image sensor has a first IC with pixels, selection transistors, and interconnect coupling selected pixels with first inter-die bond pads that convey image data to a second IC having logic and ADCs. The ADCs having inputs coupled to selected pixels and outputting through-silicon vias and inter-die bond pads to a third IC coupled to buffer raw image data in DRAM. A method includes capturing images with array pixel IC divided into sub-arrays each coupled to a separate, associated, ADC through inter-die bonds, scanning the sub-arrays and converting the image data to digital image data; and transferring the digital image data over inter-die bonds into buffers in DRAM.