I-Teh Sha

US Patent:

6404294, Jun 11, 2002

Filed:

Jul 18, 2000

Appl. No.:

09/618706

Inventors:

I-Teh Sha - Santa Clara CA
Kuang-Yu Chen - Saratoga CA
Trung Tran - Sunnyvale CA

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H03B 524

US Classification:

331 57, 331 10

Abstract:

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal having a frequency that varies in response to (i) a voltage signal and (ii) a load. The second circuit may be configured to generate the load by coupling one or more resistive devices to a reference node in response to a control signal.

US Patent:

6553057, Apr 22, 2003

Filed:

Nov 9, 1999

Appl. No.:

09/436155

Inventors:

I-Teh Sha - Santa Clara CA
Albert Chen - Saratoga CA
Kuang-Yu Chen - Saratoga CA

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H04B 169

US Classification:

375130, 375376, 327157

Abstract:

A spread spectrum clock generator comprising a spread spectrum modulation circuit and a control circuit. The spread spectrum modulation circuit may be configured to generate a clock signal in response to (i) a sequence of linearity ROM codes, (ii) a sequence of spread spectrum ROM codes, and (iii) a command signal. The control circuit may be configured to synchronize the command signal to a feedback signal. The sequence of linearity ROM codes and the sequence of spread spectrum ROM codes may be generated by predetermined mathematical formulas and optimized in accordance with predetermined criteria.

US Patent:

6850554, Feb 1, 2005

Filed:

Nov 9, 1999

Appl. No.:

09/436522

Inventors:

I-Teh Sha - Santa Clara CA, US
Kuang-Yu Chen - Saratoga CA, US
Albert Chen - Saratoga CA, US

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H03D 104

US Classification:

375140, 375139, 375149, 327148, 327157

Abstract:

A circuit and method for controlling a spread spectrum transition are presented comprising a first circuit and a second circuit. The first circuit may be configured to generate a clock signal in response to (i) a reference signal, (ii) a sequence of spread spectrum ROM codes, and (iii) a command signal. The second circuit may be configured to synchronize the command signal to a feedback signal. The sequence of spread spectrum ROM codes may be generated according to a predetermined mathematical formula and optimized in accordance with predetermined criteria.

US Patent:

6980581, Dec 27, 2005

Filed:

Jul 18, 2000

Appl. No.:

09/618622

Inventors:

I-Teh Sha - Santa Clara CA, US
Kuang-Yu Chen - Saratoga CA, US
Albert Chen - Saratoga CA, US

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H04B015/00
H04K001/00
H04L027/30

US Classification:

375130, 375367, 331 10

Abstract:

An apparatus comprising a circuit configured to generate a spread spectrum clock signal. The circuit may comprise a voltage controlled oscillator with a gain that may be automatically controlled.

US Patent:

7336112, Feb 26, 2008

Filed:

Aug 21, 2006

Appl. No.:

11/466078

Inventors:

I-Teh Sha - Cupertino CA, US
LiFeng Zhang - Shanghai, CN
HaiTao Sun - Shanghai, CN
JingRong Li - Shanghai, CN

Assignee:

Huaya Microelectronics, Ltd.

International Classification:

H03L 7/06

US Classification:

327158, 327157

Abstract:

A delay-locked loop (DLL) to produce a plurality of delayed clock signals comprising combinational logic for false lock detection is provided. The combinational logic uses only a subset of the plurality of delayed clock signals to provide a forward indicator indicating a delay period (Δt) is longer than a desired delay period. The combinational logic further provides a back indicator indicating the delay period (Δt) is shorter than a desired delay period.

US Patent:

6377646, Apr 23, 2002

Filed:

Jul 21, 1998

Appl. No.:

09/120536

Inventors:

I-Teh Sha - Santa Clara CA

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H03D 324

US Classification:

375376, 375130, 327157

Abstract:

A plurality of four bit modulation read only memory (ROM) codes are generated with a PLL feedback divider. The output of a single phase lock loop is modulated to spread the bandwidth of a synthesized clock signal. By spreading the bandwidth, the amplitude of the synthesized clock signal is decreased with respect to its fundamental and its harmonics. As a result of reducing the peak amplitudes, the radiated electromagnetic emission level is significantly lower. Input phase lock loop system data is received as to selected phase lock loop characteristics. A continuous FBD is selected, and a bandwidth and system stability calculation is performed. A state variable system is determined and a numerical model for programming by finite differences is developed. A best path is determined to produce output data and ROM code by a least squares error method.