Barry James Culpepper - Sunnyvale CA, US Jeff L. Nilles - Los Altos CA, US Chunping Song - Santa Clara CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
G05F 1/00
US Classification:
323280, 323281
Abstract:
A hysteretic regulator is provided. The hysteretic regulator includes a delay compensation circuit that adds a delay to the output of the hysteretic comparator. The delay is dependent on the input voltage. For low duty cycles, the slope of the inductor current is much greater for the rising edge than it is for the falling edge. The delay compensation circuit adds sufficient delay to the falling edge so that the undershoot cancels the overshoot.
Faruk J. Nome - Sunnyvale CA, US Jeff Lee Nilles - Los Altos CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H03F 1/02
US Classification:
330 9, 327124
Abstract:
An error amplifier for closed loop operation is provided. The error amplifier has a track input and a feedback input. During soft-start, a voltage offset is added to the error amplifier input. In one embodiment, the voltage offset is gradually removed during the soft-start.
Switching Dc-To-Dc Converter And Conversion Method With Rotation Of Control Signal Channels Relative To Paralleled Power Channels
Jeff L. Nilles - Los Altos CA Darryl Byron Phillips - Milpitas CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
G05F 140
US Classification:
323283
Abstract:
A DC-to-DC converter having multiple power channels and a switching controller which generates a pulse-width modulated control signal for each power channel, and a switching controller for use in (and a method for generating power switch control signals for) such a converter. The control signals are generated in response to trigger signal trains generated by trigger channels. The trigger channels rotate relative to the power channels so that the control signals are generated in response to a sequence of trigger channel states. In some embodiments, the controller has one control signal channel and one trigger channel for each power channel. In other embodiments, there are N power channels, N control signal channels, and M reset channels (each for generating a trigger signal train), where M is an integer greater than N. The extra channel or channels is used for preventing rotation errors which would otherwise delay opening of the closed power switches. Preferably, the sequence of trigger channel states is a periodic sequence in which each trigger channel is provided sequentially to a repeating sequence of the control signal channels, but it is alternatively a non-periodic sequence in which each trigger channel is provided equally on a time-averaged basis to each control signal channel.
Multilevel Converter Using Node Voltage Track And Control
- Dallas TX, US Jeff Lee Nilles - Los Altos CA, US Sombuddha Chakraborty - Redwood City CA, US Farzad Sahandiesfanjani - San Jose CA, US
International Classification:
H02M 1/08 H02M 3/158
Abstract:
In described examples, a system regulates provision of DC-DC electrical power. The system includes a DC-DC converter, an input voltage node to receive an input voltage, a current source, a voltage source node, and a ground switch. The DC-DC converter includes a flying capacitor and multiple converter switches. The current source is coupled between the input voltage node and a top plate of the flying capacitor, to provide current to the top plate when the current source is activated by an activation voltage. The voltage source node is coupled to the input voltage node and to the current source, to provide the activation voltage to the current source, such that the activation voltage is not higher than a selected voltage between: a breakdown voltage of the converter switches; and a maximum value of the input voltage minus the breakdown voltage. The ground switch is coupled between a bottom plate of the flying capacitor and a ground.
Resumes
Power Technologist - Distinguished Member Of Technical Staff
National Semiconductor 2004 - 2009
Power Analog Design Manager
Texas Instruments 2004 - 2009
Power Technologist - Distinguished Member of Technical Staff
Crosspoint Solutions Semiconductor 1990 - 1992
Analog Design Engineer
National Semiconductor 1990 - 1992
Analog Design Engineer
Education:
University of Wisconsin - Madison 1974 - 1979
Bachelors, Bachelor of Science In Electrical Engineering, Engineering
Skills:
Analog Circuit Design Cmos Circuit Design Semiconductors Bicmos Mixed Signal Analog Power Management Ic Asic Soc Eda Cadence Virtuoso Silicon Semiconductor Industry Integrated Circuit Design Low Power Design Hardware Architecture Semiconductor Device Pll Drc Microelectronics Physical Design Spice Lvs
Jeffrey Nilles (1991-1995), Rusty Allen (1988-1992), David Martinez (1995-1999), Melanie Martin (1989-1991), Kate Stricker (1992-1996), Frank Janecek (1989-1992)