Jeffrey D Bielefeld

US Patent:

20130260553, Oct 3, 2013

Filed:

May 13, 2013

Appl. No.:

13/893143

Inventors:

Hui Jae Yoo - Hillsboro OR, US
Jeffrey D. Bielefeld - Forest Grove OR, US
Sean W. King - Beaverton OR, US
Sridhar Balakrishnan - Portland OR, US

International Classification:

H01L 21/768

US Classification:

438643

Abstract:

Processes of forming an insulated wire into an interlayer dielectric layer (ILD) of a back-end metallization includes thermally treating a metallic barrier precursor under conditions to cause at least one alloying element in the barrier precursor to form a dielectric barrier between the wire and the ILD. The dielectric barrier is therefore a self-forming, self-aligned barrier. Thermal processing is done under conditions to cause the at least one alloying element to migrate from a zone of higher concentration thereof to a zone of lower concentration thereof to further form the dielectric barrier. Various apparatus are made by the process.

US Patent:

20220352032, Nov 3, 2022

Filed:

Jul 15, 2022

Appl. No.:

17/866122

Inventors:

- Santa Clara CA, US
Ehren MANNEBACH - Beaverton OR, US
Anh PHAN - Beaverton OR, US
Richard E. SCHENKER - Portland OR, US
Stephanie A. BOJARSKI - Beaverton OR, US
Willy RACHMADY - Beaverton OR, US
Patrick R. MORROW - Portland OR, US
Jeffrey D. BIELEFELD - Forest Grove OR, US
Gilbert DEWEY - Beaverton OR, US
Hui Jae YOO - Portland OR, US

Assignee:

INTEL CORPORATION - Santa Clara CA

International Classification:

H01L 21/8234
H01L 27/088
H01L 29/78
H01L 29/06
H01L 23/532
H01L 23/48

Abstract:

Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.