Jenny M Pelner

US Patent:

6952759, Oct 4, 2005

Filed:

Jul 28, 2003

Appl. No.:

10/628772

Inventors:

Greg E. Scott - Higley AZ, US
Jenny M. Pelner - Phoenix AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F012/00

US Classification:

711163, 711164

Abstract:

Articles, methods, apparatus, and systems to control access to a protected area of a memory are disclosed.

US Patent:

7010723, Mar 7, 2006

Filed:

Feb 11, 2002

Appl. No.:

10/073546

Inventors:

Jenny M. Pelner - Phoenix AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 11/00

US Classification:

714 36, 713 2

Abstract:

An improved method of testing a computer system comprises a sequence of tests that are performed when the computer system is first turned on, according to one embodiment. The operation of various components of the computer system, such as a chipset, a random access memory, a cache memory, a video controller, a keyboard controller, peripheral memory controllers, busses, and the like, is tested by a test program stored in read only memory (ROM). If the components successfully pass, an address is permanently changed in ROM, so that the test sequence is bypassed whenever the computer system is subsequently booted, saving significant time during future reboots. An improved computer system and a machine-accessible medium are also described.

US Patent:

20030023822, Jan 30, 2003

Filed:

Jul 11, 2001

Appl. No.:

09/902998

Inventors:

Greg Scott - Higley AZ, US
Jenny Pelner - Phoenix AZ, US

Assignee:

Intel Corporation

International Classification:

G06F012/14

US Classification:

711/163000

Abstract:

Methods, circuitry, an apparatus, and a system for controlling access to a protected area of a memory are disclosed. The method includes detecting an attempt to write to the protected area, determining whether a write authorization flag (not located in the protected area) has been set by instructions located in the protected area, and, if the flag has been set, enabling the attempted write operation. The circuitry, apparatus, and system embody the method in various combinations of software and hardware, such that a write detection module alerts a processor module regarding attempts to write to the protected area, the processor module determines whether the write operation has been authorized by checking the state of the authorization flag, and enables the write operation to the protected area only if the authorization flag has been set.

US Patent:

20210326142, Oct 21, 2021

Filed:

Jun 27, 2020

Appl. No.:

16/914331

Inventors:

SUBRATA BANIK - Bangalore, IN
ASAD AZAM - EL DORADO HILLS CA, US
JENNY M. PELNER - Phoenix AZ, US
VINCENT ZIMMER - ISSAQUAH WA, US
RAJARAM REGUPATHY - Bangalore, IN

International Classification:

G06F 9/4401
G06F 12/0802

Abstract:

Systems, methods, and apparatuses relating to circuitry to implement a multiprocessor boot flow for a faster boot process are described. In one embodiment, a system includes a hardware processor comprising a processor core, a cache coupled to the hardware processor, storage for hardware initialization code, and a controller circuit to initialize a portion of the cache as memory for usage by the hardware initialization code before beginning execution of the hardware initialization code after a power on of the system.