Jerry L Kindell

US Patent:

42850355, Aug 18, 1981

Filed:

Jan 2, 1979

Appl. No.:

6/000221

Inventors:

Jerry L. Kindell - Glendale AZ
Richard T. Flynn - Peoria AZ

Assignee:

Honeywell Information Systems Inc. - Phoenix AZ

International Classification:

G06F 930

US Classification:

364200

Abstract:

In a microprogrammed data processing system in which the boundaries of the operands or data strings identified by the descriptors are not constrained to coincide with boundaries of the units of addressable memory space, i. e. , words, the time required to retrieve, execute and store operands of a three descriptor instruction, wherein two descriptors define the memory address of the initial operands and the third descriptor defines the memory address of the resulting operand, can be reduced by prefetching the two words which include the boundaries of the operand (data string) identified by the third descriptor. After execution of the instruction, the boundary words of the resulting operand (data string) can have the rewrite data, that is the data of the boundary words which are not part of the resulting operand, and should therefore be retained and inserted in appropriate positions of the appropriate boundary word by a retrieval of the boundary words which do not interrupt the normal data processing sequence.

US Patent:

42401445, Dec 16, 1980

Filed:

Jan 2, 1979

Appl. No.:

6/000399

Inventors:

Jerry L. Kindell - Glendale AZ
Richard T. Flynn - Peoria AZ

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 922

US Classification:

364200

Abstract:

In a microprogrammed data processing system, the throughput of the system is increased during the processing of decimal numeric instructions by apparatus which receives a long operand, greater than a predetermined number of words, which is the result of the calculation, assembles the resultant operand in accordance with an instruction descriptor, and transfers the resultant operand to memory.

US Patent:

44082711, Oct 4, 1983

Filed:

Dec 22, 1980

Appl. No.:

6/219196

Inventors:

Jerry L. Kindell - Glendale AZ

Assignee:

Honeywell Information Systems Inc. - Phoenix AZ

International Classification:

G06F 500
G06F 300

US Classification:

364200

Abstract:

Apparatus for implementing a single computer instruction for moving a binary number of from one to four characters, with the characters of a given binary number having either eight or nine bits per character, from storage in a word addressable memory to a designated addressable register. The characters of the binary number are stored in the word addressable memory with each word of memory being divided into four 9-bit bytes. The most significant character of the binary number can be stored in any designated byte position of a word location with the characters of the number stored in contiguous byte locations in descending order of significance. The apparatus causes the binary number to be stored in the designated addressable register with the binary number being right justified in that register. Higher order bit positions of the register not needed to store the bits of the binary number will have stored into them fill bits or the sign bit of the number.

US Patent:

43216684, Mar 23, 1982

Filed:

Jan 2, 1979

Appl. No.:

6/000223

Inventors:

Richard T. Flynn - Peoria AZ
Jerry L. Kindell - Glendale AZ

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 934

US Classification:

364200

Abstract:

A microprogrammed data processing system includes a cache memory, a decimal unit and an execution unit. The decimal unit receives operands from cache memory, strips the non-decimal digit information from the operands, and assembles the 4-bit decimal digits from the operand into words containing a maximum of 8 decimal digits for transfer to the execution unit. The execution unit processes the words in accordance with a decimal numeric instruction. The throughput of the system is increased when processing short operands which contain 15 decimal digits or less by apparatus in the decimal unit which detects the short operand and determines the number of cache memory cycles between the cycle the first word of the short operand is received from cache memory and the cycle on which the first assembled word is transferred to the execution unit for processing.

US Patent:

42518644, Feb 17, 1981

Filed:

Jan 2, 1979

Appl. No.:

6/000393

Inventors:

Jerry L. Kindell - Glendale AZ
Richard T. Flynn - Peoria AZ

Assignee:

Honeywell Information Systems Inc. - Phoenix AZ

International Classification:

G06F 300

US Classification:

364200

Abstract:

In a data processing system wherein memory space in a memory unit is divided into addressable locations capable of storing a group of signals of predetermined number called signal words, and wherein an entire word or groups of entire words are exchanged between the memory unit and a central processing unit, more efficient operation of the data processing unit can be obtained if groups of related signals called operands can be stored consecutively in the addressable locations without regard to the word boundaries. Thus, operand boundaries can have arbitrary positions in boundary words. When a word containing an operand boundary is transferred to the central processing unit, non-operand data is also transferred with the word. The non-operand data occurring in the boundary words is removed from the operand signal group and stored in the central processing unit. After manipulation of the operand by the central processing unit, the non-operand data is re-inserted in the boundary words in the signal positions previously occupied and the word group containing the manipulation or resulting operand is stored in the memory location from which it was originally removed.

US Patent:

40412920, Aug 9, 1977

Filed:

Dec 22, 1975

Appl. No.:

5/642844

Inventors:

Jerry L. Kindell - Phoenix AZ

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 752

US Classification:

235164

Abstract:

A multiplication apparatus comprises a plurality of multiple generator circuits, each of which simultaneously generates binary signals representative of a predetermined multiple of a multiplicand for different digits of a group of multiplier digits. A different one of the multiple generator circuits couples to a different one of a plurality of serially connected adder circuits for applying the binary signals. Each of the multiple generator circuits includes storage circuits coupled to receive timing signals from a common source to enable an overlap in the generation of binary multiple signals minimizing the number of multiplication cycles required to perform a multiplication operation in response to multiply instructions.

US Patent:

42246776, Sep 23, 1980

Filed:

Jan 2, 1979

Appl. No.:

6/000222

Inventors:

Jerry L. Kindell - Glendale AZ
Richard T. Flynn - Peoria AZ

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 100
G06F 700
G06F 1300

US Classification:

364715

Abstract:

In a microprogrammed data processing system, the throughput of the system is increased by apparatus which counts the number of effective digits in an operand which is the result of a decimal numeric instruction being processed by the system. The apparatus receives operand words the operand's least significant word first, in response to a predetermined microword. The apparatus includes a first register which stores a count of one less than the number of words received; an adder which increments the output of the first register if the word received has a decimal zero in the high order position of the word; and a second register which stores the output of the adder in a word count portion and the number of leading zeros in a digit count portion of the second register. The second register is loaded on the same cycle the word is processed providing the word does not contain all decimal zeros.

US Patent:

42478910, Jan 27, 1981

Filed:

Jan 2, 1979

Appl. No.:

6/000232

Inventors:

Richard T. Flynn - Peoria AZ
Jerry L. Kindell - Glendale AZ

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 738

US Classification:

364200

Abstract:

In a microprogrammed data processing system, the throughput of the system is increased by apparatus which counts the number of leading zero digits of an operand on the cycle in which the operand word is processed through the decimal unit and sends that count to the execution unit in response to a predetermined microword. The apparatus counts the number of leading zero digits by first storing in a register the number of words the decimal unit will not send for processing as determined by an instruction descriptor. As the operand is received by the decimal unit, most significant word first, the number of leading zero digits in the operand is added to the register on the same cycle the operand word is processed through the decimal unit, thereby generating a count of the number of zero digits in the operand that the decimal unit will send for processing. This leading zero digit count is available to the firmware in response to a microword command.